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| Features Datasheet RX62N/RX621 Group RENESAS 32-Bit MCU R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 100 MHz 32-bit RX MCU with FPU, 165 DMIPS, up to 512-Kbyte Flash, Ethernet, USB 2.0 Full-Speed Host/Function/OTG, CAN, 12-bit ADC, TFT-LCD, RTC, up to 14 communication channels Features 32-bit RX CPU Core Delivers 165 DMIPS at a maximum operating frequency of 100 MHz Single Precision 32-bit IEEE-754 Floating Point Accumulator: 32 x 32 to 64-bit result, one instruction Mult/Divide Unit, 32 x 32 Multiply in one CPU clock for multiple instructions Interrupt response in as few as 5 CPU clock cycles CISC-Harvard Architecture with 5-stage pipeline Variable length instructions, ultra compact code Supports the Memory Protection Unit (MPU) Background JTAG debug plus high-speed trace TFLGA85 7x7mm, 0.65mm pitch TFLGA145 9x9mm, 0.65mm pitch LFBGA176 13x13mm, 0.8mm pitch LQFP100 14x14mm, 0.5mm pitch LQFP144 20x20mm, 0.5mm pitch Up to 14 Communication Interfaces (2) USB 2.0 Full-Speed interfaces with PHY Supports Host/Function/OTG 10 endpoints for types: Control, Interrupt, Bulk, Isochronous (1) Ethernet MAC 10/100 Mbps, Half or Full Duplex Supported. Dedicated DMA with 2-Kbyte transmit and receive FIFOs. RMII or MII interface to external PHY (1) CAN ISO11898-1, supports 32 mailboxes (6) SCI channels: Asynchronous, clock sync, smartcard, and 9-bit modes (2) I2C interfaces up to 1M bps, SMBus support (2) RSPI Low Power Design and Architecture 2.7V to 3.6V operation from a single supply 480 A/MHz Run Mode with all peripherals on Deep Software Standby Mode with RTC Four low power modes Main Flash Memory, no Wait-State 100 MHz operation, 10 nsec read cycle No wait states for read at full CPU speed 256K, 384K, 512K Byte size options For Instructions or Operands Programming from USB, SCI, JTAG, user code Data Flash Memory Up to 32K Bytes with 30K Erase Cycles Background Erase/Program does not stall CPU External Address Space Eight CS areas (8 x 16 Mbytes) 128-Mbyte SDRAM area 8-/16-/32-bit bus space selectable for each area SRAM, no Wait-State 64K or 96K Byte size options For Operands or Instructions Back-up retention in Deep Software Standby Mode TFT-LCD up to WQVGA resolution Up to 20 Extended Function Timers (12) 16-bit MTU2 Input capture, Output Compare, PWM output, phase count mode (4) 8-bit TMR (4) 16-bit CMT DMA Four fully programmable internal DMA channels Two EXDMA channels for external-to-external transfers Data Transfer Controller (DTC) Reset and Supply Management Power-On Reset (POR) monitor/generator Low Voltage Detect (LVD) with precision setting 1-MHz ADC units with two combination choices 12-bit x 8 ch. unit with single sample/hold circuit or (2) 10-bit x 4 ch units each with a sample/hold circuit AD-converted value addition mode (12-bit A/D converter) System Clocking with Clock Monitoring External crystal, 8 MHz to 14 MHz to Internal PLL PLL source to system, USB, and Ethernet Internal 125 kHz LOCO for IWDT External crystal, 32 kHz for RTC 10-bit DAC, 2 channels Up to 128 GPIO 5V tolerant, Open-Drain, Internal Pull-up Real Time Clock Full calendar function, BCD format Operation Temp -40C to +85C Two Independent Watchdog Timers 125-kHz LOCO operation R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 1 of 146 RX62N Group, RX621 Group 1. Overview 1. 1.1 Overview Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 lists the functions of products. Table 1.1 Classification CPU Outline of Specifications (1 / 4) Module/Function CPU Description * * * * * * * * * * * * * * * * * * * RAM Data flash MCU operating modes Clock Clock generation circuit Maximum operating frequency: 100 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Nine 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 Floating-point instructions: 8 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 x 32 64 bits On-chip divider: 32 / 32 32 bits Barrel shifter: 32 bits Memory-protection unit (MPU) (as an optional function)*1 Single precision (32-bit) floating point Data types and floating-point exceptions in conformance with the IEEE754 standard ROM capacity: 512 Kbytes (max.) Two on-board programming modes Boot mode (The user MAT is programmable via the SCI and USB.) User program mode Parallel programmer mode (for off-board programming) FPU Memory ROM RAM capacity: 96 Kbytes (max.) Data flash capacity: 32 Kbytes * * * * * * Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled expansion mode (software switching) Two circuits: Main clock oscillator and subclock oscillator Internal oscillator: Low-speed on-chip oscillator Structure of a PLL frequency synthesizer and frequency divider for selectable operating frequency Oscillation stoppage detection Independent frequency-division and multiplication settings for the system clock (ICLK), peripheral module clock (PCLK), and external bus clock (BCLK) The CPU and other bus masters run in synchronization with the system clock (ICLK): 8 to 100 MHz Peripheral modules run in synchronization with the peripheral module clock (PCLK): 8 to 50 MHz Devices connected to the external bus run in synchronization with the external bus clock (BCLK): 8 to 50 MHz Pin reset, power-on reset, voltage-monitoring reset, watchdog timer reset, independent watchdog timer reset, and deep software standby reset When the voltage on VCC falls below the voltage detection level (Vdet), an internal reset or internal interrupt is generated. Module stop function Four low power consumption modes Sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode * Reset Voltage detection circuit Low power consumption Low power consumption facilities * * * * R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 2 of 146 RX62N Group, RX621 Group Table 1.1 Classification Interrupt 1. Overview Outline of Specifications (2 / 4) Module/Function Interrupt control unit Description * * * * * * * Peripheral function interrupts: 146 sources External interrupts: 16 (pins IRQ0 to IRQ15) Non-maskable interrupts: 3 (the NMI pin, oscillation stop detection interrupt, and voltagemonitoring interrupt) Sixteen levels specifiable for the order of priority Two breakpoint channels Address breaks in fetch cycles are specifiable (enabling ROM correction) The external address space can be divided into nine areas (CS0 to CS7, SDCS), each with independent control of access settings. Capacity of each area: 16 Mbytes (CS0 to CS7), 128 Mbytes (SDCS) A chip-select signal (CS0# to CS7#, SDCS#) can be output for each area. Each area is specifiable as an 8-, 16-, or 32-bit bus space (however, only 176-pin versions support 32-bit bus spaces). The data arrangement in each area is selectable as little or big endian (only for data). SDRAM interface connectable Bus format: Separate buses Wait control Write buffer facility 4 channels Three transfer modes: Normal transfer, repeat transfer, and block transfer Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral functions 2 channels Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster transfer Single-address transfer enabled with the EDACK signal Capable of direct data transfer to TFT LCD panels Activation sources: Software trigger, external DMA requests (EDREQ), and interrupt requests from peripheral functions Three transfer modes: Normal transfer, repeat transfer, and block transfer Activation sources: Software trigger, external interrupts and interrupt requests from peripheral functions I/O ports for the 176-pin LFBGA/145-pin TFLGA/144-pin LQFP/100-pin LQFP/85-pin TFLGA I/O pins: 126/103/103/72/58 Input pins: 2/2/2/2/2 Pull-up resistors: 56/44/44/40/28 Open-drain outputs: 35/33/33/27/23 5-V tolerance: 11/11/11/7/6 (16 bits x 6 channels) x 2 units Time bases for the 12 16-bit timer channels can be provided via up to 32 pulse-input/ output lines and six pulse-input lines Select from among eight counter-input clock signals for each channel (PCLK/1, PCLK/4, PCLK/16, PCLK/64, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than channel 5, for which only four signals are available. Input capture function 21 output compare/input capture registers Pulse output mode Complementary PWM output mode Reset synchronous PWM mode Phase-counting mode Generation of triggers for A/D converter conversion Controls the high-impedance state of the MTU's waveform output pins User break controller (as an optional function) External bus extension DMA DMA controller * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * EXDMA controller Data transfer controller I/O ports Programmable I/O ports Timers Multi-function timer pulse unit Port output enable R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 3 of 146 RX62N Group, RX621 Group Table 1.1 Classification Timers 1. Overview Outline of Specifications (3 / 4) Module/Function Programmable pulse generator 8-bit timers Description * * * * * * * * * * * * * * * * * * * * * * * * (4 bits x 4 groups) x 2 units Pulse output with the MTU output as a trigger Maximum of 32-bit pulse output possible (8 bits x 2 channels) x 2 units Select from among seven internal clock signals (PCLK, PCLK/2, PCLK/8, PCLK/32, PCLK/64, PCLK/1024, PCLK/8192) and one external clock signal Capable of output of pulse trains with desired duty cycles or of PWM signals The 2 channels of each unit can be cascaded to create a 16-bit timer Generation of triggers for A/D converter conversion Capable of generating baud-rate clocks for SCI5 and SCI6 (16 bits x 2 channels) x 2 units Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512) 8 bits x 1 channel Select from among eight counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/512, PCLK/2048, PCLK/8192, PCLK/32768, PCLK/131072) Switchable between watchdog timer mode and interval timer mode 14 bits x 1 channel Counter-input clock: Dedicated on-chip oscillator Clock source: Subclock Time/calendar Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt Input and output of Ethernet/IEEE 802.3 frames Transfer at 10 or 100 Mbps Full- and half-duplex modes MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as defined in IEEE 802.3u Detection of Magic PacketsTM* or output of a "wake-on-LAN" signal (WOL) Compliance with flow control as defined in IEEE 802.3x standards Alleviation of CPU loads by the descriptor control method Transmission FIFO: 2 Kbytes; Reception FIFO: 2 Kbytes Includes a UDC (USB Device Controller) and transceiver for USB 2.0 Single port (176-pin products: two ports) Compliance with the USB 2.0 specification Transfer rate: Full speed (12 Mbps) Self-power mode and bus power are selectable OTG (On the Go) operation is possible Incorporates 2 Kbytes of RAM as a transfer buffer 6 channels Serial communications modes: Asynchronous, clock synchronous, and smart-card interface Multi-processor communications function On-chip baud rate generator allows selection of the desired bit rate Choice of LSB-first or MSB-first transfer Average transfer rate clock can be input from TMR timers for SCI5 and SCI6 Compare match timer Watchdog timer Independent watchdog timer Realtime clock Communication function Ethernet controller Note: * Magic PacketTM is a registered trademark of Advanced Micro Devices, Inc. DMA controller for Ethernet controller USB 2.0 host/ function module Serial communications interfaces * * * * * * * * * * * * * * * R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 4 of 146 RX62N Group, RX621 Group Table 1.1 Classification Communication function 1. Overview Outline of Specifications (4 / 4) Module/Function I2C bus interfaces Description * * * * * * 2 channels (100-pin version: 1 channel) Communications formats I2C bus format/SMBus format Master/slave selectable (For multi-master operation) 1 channel 32 mailboxes 2 channels RSPI transfer facility Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clock-synchronous operation (three lines) Capable of handling serial transfer as a master or slave Data formats Switching between MSB first and LSB first The number of bits in each transfer can be changed to any number of bits from 8 to 16, or to 20, 24, or 32 bits. 128-bit buffers for transmission and reception Up to four frames can be transmitted or received in a single transfer operation (with each frame having up to 32 bits) Buffered structure Double buffers for both transmission and reception 12 bits x 1 unit (1 unit x 8 channels) or 10 bits x 2 units (2 units x 4 channels); 12- and 10-bit A/D converters can be exclusively used. 10- or 12-bit resolution Conversion time: 1.0 s per channel (in operation with PCLK at 50 MHz) Two operating modes Single mode Scan mode (one-cycle scan mode or continuous scan mode) Sample-and-hold function Three ways to start A/D conversion Conversion can be started by software, a conversion start trigger from a timer (MTU or TMR), or an external trigger signal. Self-diagnostic functions 2 channels (1 channel for 100-pin products) 10-bit resolution Output voltage: 0 V to VREFH CRC code generation for arbitrary amounts of data in 8-bit units Select any of three generating polynomials: X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1. Generation of CRC codes for use with LSB-first or MSB-first communications is selectable. CAN module Serial peripheral interfaces * 12-bit A/D converter 10-bit A/D converter * * * * * * * * * * * * * * * D/A converter CRC calculator Operating frequency Power supply voltage Operating temperature Package 8 to 100 MHz VCC = PLLVCC = AVCC = 2.7 to 3.6V, VREFH = 2.7 to AVCC 40 to +85C 176-pin LFBGA (PLBG0176GA-A), 145-pin TFLGA (PTLG0145JB-A), 144-pin LQFP (PLQP0144KA-A), 100-pin LQFP (PLQP0100KB-A)*2 85-pin TFLGA (PTLG0085JA-A)*2, * 3 Note 1. As for the MPU, contact your Renesas sales agency. Note 2. For products in the 100-pin LQFP and 85-pin TFLGA, BCLK is synchronized with 8 to 25 MHz. Note 3. MSB-first order is only available in the smart-card interface mode. R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 5 of 146 RX62N Group, RX621 Group 1. Overview Table 1.2 Functions Functions of RX62N Group and RX621 Group Products RX62N Group R5F562NxBxxx* 176-pin LFBGA 145-pin TFLGA R5F562NxAxxx* 176-pin LFBGA 145-pin TFLGA RX621 Group R5F5621xBxxx* 176-pin LFBGA 145-pin TFLGA Package External bus DMA SDRAM area controller DMA controller EXDMA controller Data transfer controller Timers Multi-function timer pulse unit Port output enable Programmable pulse generator 8-bit timers Compare match timer Realtime clock Watchdog timer Independent watchdog timer Communication function Ethernet controller/ DMA controller for Ethernet controller USB 2.0 host/function module Serial communications interfaces I2C bus interfaces CAN module Serial peripheral interfaces A/D converter D/A converter CRC calculator O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O ae O O O O O O O O O O O O O O O O O O O O O O O O [Legend] O: Supported, : Not supported Note: * For details on part numbers, see Table 1.3. R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 6 of 146 85-pin TFLGA 144-pin LQFP 100-pin LQFP 144-pin LQFP 100-pin LQFP 144-pin LQFP 100-pin LQFP RX62N Group, RX621 Group 1. Overview 1.2 List of Products Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no. Table 1.3 List of Products Operating Frequency (Max.) 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz Group RX62N Part No. R5F562N8BDBG R5F562N8BDLE R5F562N8BDFB R5F562N8BDFP R5F562N7BDBG R5F562N7BDLE R5F562N7BDFB R5F562N7BDFP R5F562N8ADBG R5F562N8ADLE R5F562N8ADFB R5F562N8ADFP R5F562N7ADBG R5F562N7ADLE R5F562N7ADFB R5F562N7ADFP Package PLBG0176GA-A PTLG0145JB-A PLQP0144KA-A PLQP0100KB-A PLBG0176GA-A PTLG0145JB-A PLQP0144KA-A PLQP0100KB-A PLBG0176GA-A PTLG0145JB-A PLQP0144KA-A PLQP0100KB-A PLBG0176GA-A PTLG0145JB-A PLQP0144KA-A PLQP0100KB-A PLBG0176GA-A PTLG0145JB-A PLQP0144KA-A PLQP0100KB-A PTLG0085JA-A PLBG0176GA-A PTLG0145JB-A PLQP0144KA-A PLQP0100KB-A PTLG0085JA-A PLBG0176GA-A PTLG0145JB-A PLQP0144KA-A PLQP0100KB-A PTLG0085JA-A ROM Capacity 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 384 Kbytes 384 Kbytes 384 Kbytes 384 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 384 Kbytes 384 Kbytes 384 Kbytes 384 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 384 Kbytes 384 Kbytes 384 Kbytes 384 Kbytes 384 Kbytes 256 Kbytes 256 Kbytes 256 Kbytes 256 Kbytes 256 Kbytes RAM Capacity 96 Kbytes 96 Kbytes 96 Kbytes 96 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 96 Kbytes 96 Kbytes 96 Kbytes 96 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 96 Kbytes 96 Kbytes 96 Kbytes 96 Kbytes 96 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Data Flash 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes RX621 R5F56218BDBG R5F56218BDLE R5F56218BDFB R5F56218BDFP R5F56218BDLD R5F56217BDBG R5F56217BDLE R5F56217BDFB R5F56217BDFP R5F56217BDLD R5F56216BDBG R5F56216BDLE R5F56216BDFB R5F56216BDFP R5F56216BDLD R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 7 of 146 RX62N Group, RX621 Group 1. Overview R5F5 62N 7BDBG Indicates the package type, number of pins, and pin pitch . BG: LFBGA176-0.80 LE: TFLGA145-0.65 FB: LQFP144-0.50 FP: LQFP100-0.50 LD: TFLGA85-0.65 A: The CAN module is not included. B: CAN x 1 channel Indicates the ROM capacity, RAM capacity, and data flash capacity. 8: 512 Kbytes/96 Kbytes/32 Kbytes 7: 384 Kbytes/64 Kbytes/32 Kbytes 6: 256 Kbytes/64 Kbytes/32 Kbytes Indicates a group name 2N: RX62N group 21: RX621 group Indicates the RX600 Series. Indicates the type of memory. F: Flash memory version Indicates a Renesas MCU. Indicates a Renesas semiconductor product. Figure 1.1 How to Read the Product Part No. R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 8 of 146 RX62N Group, RX621 Group 1. Overview 1.3 Block Diagram Figure 1.2 shows a block diagram. Data flash WDT IWDT CRC SCI x 6ch USB (up to 2 ports) * RSPI (unit 0) RSPI (unit 1) CAN *1 MTU x 6 channels (unit 0) 2 Internal peripheral bus 1 to 6 * 1 *1 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port C Port D Port E Port F MTU x 6 channels (unit 1) POE * 1 * ETHERC 1 PPG (unit 0) PPG (unit 1) TMR x 2 channels (unit 0) TMR x 2 channels (unit 1) * EDMAC ICU ROM Internal main bus 2 1 CMT x 2 channels (unit 0) CMT x 2 channels (unit 1) RTC DTC DMACA bus RAM Instruction Operand bus RIIC x 2 channels * 3 12-bit A/D converter x 8 channels x 4 channels (unit 0) 10-bit A/D converter x 4 channels (unit 1) 10-bit A/D converter Internal main bus 1 RX CPU MPU Clock generation circuit 10-bit D/A converter x 2 channels * *1 EXDMAC BSC External bus 3 Port G Notes: 1. The installation of the EXDMAC, EtherC, EDMAC, USB, CAN module, POE, and ports 0 to G is different depending on the product group and package. 2. For detail on the bus configuration of internal peripheral buses, see section 12, Buses. 3. The number of RIIC units and 10-bit D/A converter channels that are incorporated differs with the package. Ethernet controller DMA controller for Ethernet controller Interrupt control unit Data transfer controller DMA controller EXDMA controller Bus controller Watchdog timer Independent watchdog timer CRC (Cyclic Redundancy Check) calculator Memory-protection unit SCI: USB: RSPI: CAN: MTU: POE: PPG: TMR: CMT: RTC: RIIC: Serial communications interfaces USB 2.0 host/function module Serial peripheral interfaces CAN module Multi-function timer pulse unit Port output enable Programmable pulse generator 8-bit timer Compare match timer Realtime clock I2C bus interface ETHERC: EDMAC: ICU: DTC: DMACA: EXDMAC: BSC: WDT: IWDT: CRC: MPU: Figure 1.2 Block Diagram R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 9 of 146 RX62N Group, RX621 Group 1. Overview 1.4 Pin Assignments Figure 1.3 to Figure 1.9 show the pins assignments. Table 1.4 to Table 1.8 show the list of pins and pin functions. A B C D E F G H J K L M N P R 15 PE1 P70 PE6 P65 P67 PG5 PA1 PA3 PA6 PB0 VCC PB2 PB5 PB7 P75 15 14 P63 PE2 PE5 PE7 P66 PA0 PG6 PA4 PA7 P72 PB3 PB6 P73 PC1 P77 14 13 P61 P64 PE3 PE4 VCC PG3 VCC PA2 PA5 P71 PB4 VCC P74 P76 P80 13 12 PD7 P62 PE0 VSS PG2 PG4 VSS PG7 VSS PB1 VSS PC0 PC2 PC4 PC7 12 11 PG0 P60 VCC VSS P81 PC3 P82 P83 11 10 PD4 PD6 PD5 PG1 PC6 PC5 P50 P53 10 9 PD3 P97 VCC VSS 8 PD2 P96 P94 P95 7 PD0 PD1 P92 P93 RX62N Group RX621 Group PLBG0176GA-A (176-pin LFBGA) (Upper perspective view) VSS VCC P84 P85 9 P51 P52 VCC_ USB USB1_ DP USB1_ DM VSS_ USB USB0_ DP USB0_ DM 8 P54 P10 P56 7 6 P90 P91 VCC VSS P55 P57 VCC_ USB 6 5 P46 P47 P40 P43 P11 P15 P13 5 4 P45 P44 P07 P41 VSS VSS MDE RES# P34 PF4 P30 VSS P17 P14 4 3 P42 VREFL P05 VCC BSCANP VCL MD0 VCC PF3 PF0 VCC P22 P20 P16 P12 3 2 AVCC VREFH P03 P01 CNVSS WDTOVF# MD1 P35 P32 P31 P27 P25 P23 PLLVCC PLLVSS 2 1 AVSS P02 P00 EMLE XCIN XCOUT VSS XTAL EXTAL P33 PF2 PF1 P26 P24 P21 1 A B C D E F G H J K L M N P R : NC pin Figure 1.3 Pin Assignment of the 176-Pin LFBGA R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 10 of 146 RX62N Group, RX621 Group 1. Overview A B C D E F G H J K L M N 13 P64 PE4 P70 PE6 P66 PA2 PA4 PA7 P72 PB3 PB6 VSS P74 13 12 P62 PE1 PE3 PE7 PA0 VCC PA6 PB1 PB5 PC0 VCC PC1 P76 12 11 P60 PE2 PE5 VCC P67 PA3 PA5 P71 PB4 P73 P75 PC2 PC4 11 10 PD6 PE0 P63 VSS P65 PA1 VSS PB0 PB2 PB7 P77 P80 PC5 10 9 PD3 VSS P61 VCC PC3 P81 PC6 VCC 9 8 PD0 PD5 PD7 PD4 7 P91 PD1 PD2 P93 6 P47 P90 P92 VSS RX62N Group RX621 Group PTLG0145JB-A (145-pin TFLGA) (Upper perspective view) NC P82 P83 P50 P51 8 PC7 P52 P55 P54 7 VSS P56 VSS_ USB USB0_ DP 6 5 P44 P45 P46 VCC P53 VCC_ USB P14 USB0_ DM 5 4 P42 P40 P41 P43 BSCANP MDE MD0 RES# P32 P26 P12 P15 P13 4 3 VREFL VREFH VSS P02 P00 WDTOVF# MD1 VCC P35 P31 P17 PLLVCC PLLVSS 3 2 AVCC P07 P05 VCC VSS XCOUT VSS P34 P27 P24 P22 P20 P16 2 1 AVSS P03 P01 EMLE VCL XCIN XTAL EXTAL P33 P30 P25 P23 P21 1 A B C D E F G H J K L M N : NC pin Figure 1.4 Pin Assignment of the 145-Pin TFLGA R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 11 of 146 RX62N Group, RX621 Group 1. Overview 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 PE2/D10/SSLB3-B/POE9# PE1/D9/SSLB2-B PE0/D8/SSLB1-B P64/CS4#-A/WE# P63/CS3#-A/CAS# P62/CS2#-A/RAS# P61/CS1#-A/SDCS# VSS P60/CS0#-A VCC PD7/D7/MTIC5U/POE0# PD6/D6/MTIC5V/POE1# PD5/D5/MTIC5W/POE2# PD4/D4/MTIC11U-B/POE3# PD3/D3/MTIC11V-B/POE4# PD2/D2/MTIC11W-B/POE5# PD1/D1/POE6# PD0/D0/POE7# P93/A19-B P92/A18-B P91/A17-B VSS P90/A16-B VCC P47/AN7/IRQ15-B P46/AN6/IRQ14 P45/AN5/IRQ13-B P44/AN4/IRQ12 P43/AN3/IRQ11-B P42/AN2/IRQ10-B P41/AN1/IRQ9-B VREFL P40/AN0/IRQ8-B VREFH AVCC P07/ADTRG0#-A/IRQ15-A 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 73 72 71 70 69 68 67 66 65 64 63 62 61 60 PC1/A17-A/MTCLKH-A/SCK5/SSLA2-A/ET_ERXD2 PC0/A16-A/MTCLKG-A/SSLA1-A/ET_ERXD3 VCC PA0/A0/BC0#/PO16/MTIOC6A/SSLA1-B PB4/A12/PO28/MTIOC10A/MTCLKE-B PB5/A13/PO29/MTIOC10C/MTCLKF-B PB2/A10/PO26/MTIOC9B/MTCLKG-B PB3/A11/PO27/MTIOC9D/MTCLKH-B PA5/A5/PO21/MTIOC7B/RSPCKA-B PA6/A6/PO22/MTIOC8A/MOSIA-B PA7/A7/PO23/MTIOC8B/MISOA-B PA1/A1/PO17/MTIOC6B/SSLA2-B PA2/A2/PO18/MTIOC6C/SSLA3-B PA4/A4/PO20/MTIOC7A/SSLA0-B VCC PE5/D13/RSPCKB-B/IRQ5-A VSS PE6/D14/MOSIB-B/IRQ6-A PE7/D15/MISOB-B/IRQ7-A PB6/A14/PO30/MTIOC10B PB7/A15/PO31/MTIOC10D P73/CS3#-B/ET_WOL PA3/A3/PO19/MTIOC6D VSS P72/CS2#-B/ET_MDC PB1/A9/PO25/MTIOC9C PB0/A8/PO24/MTIOC9A P71/CS1#-B/ET_MDIO P66/CS6#-A/DQM0 P67/CS7#-A/DQM1 PE4/D12/SSLB0-B P65/CS5#-A/CKE PE3/D11/POE8# P70/SDCLK VCC VSS P74/CS4#-B/ET_ERXD1/RMII_RXD1 P75/CS5#-B/ET_ERXD0/RMII_RXD0 PC2/A18-A/MTCLKE-A/RxD5/SSLA3-A/ET_RX_DV P76/CS6#-B/ET_RX_CLK/REF50CK P77/CS7#-B/ET_RX_ER/RMII_RX_ER PC3/A19-A/MTCLKF-A/TxD5/ET_TX_ER PC4/A20/CS3#-C/MTCLKC-B/SSLA0-A/ET_TX_CLK P80/EDREQ0-A/MTIOC3B-B/ET_TX_EN/RMII_TXD_EN/TRDATA0 P81/EDACK0-A/MTIOC3D-B/ET_ETXD0/RMII_TXD0/TRDATA1 P82/EDREQ1-A/MTIOC4A-B/ET_ETXD1/RMII_TXD1/TRSYNC PC5/A21/CS2#-C/WAIT#-C/MTIC11W-A/MTCLKD-B/RSPCKA-A/ET_ETXD2 PC6/A22/CS1#-C/MTIC11V-A/MTCLKA-B/MOSIA-A/ET_ETXD3 PC7/A23/CS0#-B/MTIC11U-A/MTCLKB-B/MISOA-A/ET_COL VCC P83/EDACK1-A/MTIOC4C-B/ET_CRS/RMII_CRS_DV/TRCLK VSS P50/WR0#/WR#/TxD2-B/SSLB1-A P51/WR1#/BC1#/WAIT#-D/SCK2/SSLB2-A P52/RD#/RxD2-B/SSLB3-A P53/BCLK P54/EDACK0-C/MTIOC4B-B/ET_LINKSTA/TRDATA2 P55/WAIT#-B/EDREQ0-C/MTIOC4D-B/ET_EXOUT/TRDATA3 P56/EDACK1-C/MTIOC3C-B VSS_USB USB0_DP USB0_DM VCC_USB P12/TMCI1-B/RxD2-A/SCL0/IRQ2-B P13/ADTRG1#/TMO3/TxD2-A/SDA0/IRQ3-B P14/TMRI2/IRQ4-B/USB0_OVRCURA/USB0_DPUPE-B P15/PO13/MTIOC0B/TMCI2-A/SCK3-A/IRQ5-B PLLVSS P16/PO14/MTIOC3C-A/TMO2/RxD3-A/IRQ6-B/USB0_VBUS/USB0_OVRCURB/USB0_VBUSEN-B PLLVCC P17/PO15/MTIOC3A/TxD3-A/IRQ7-B P20/PO0/MTIOC1A/TMRI0-B/TxD0/SDA1/USB0_ID RX62N Group RX621 Group PLQP0144KA-A (144-pin LQFP) (Top view) 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 XCOUT RES# VCC XCIN VCC P27/CS7#-C/PO7/MTIOC2B/SCK1/RSPCKB-A/TCK P26/CS6#-C/PO6/MTIOC2A/TMO1/TxD1/MOSIB-A/TDO P25/CS5#-C/EDACK1-B/ADTRG0#-B/PO5/MTIOC4C-A/MTCLKB-A/RxD3-B/USB0_DPRPD P24/CS4#-C/EDREQ1-B/PO4/MTIOC4A-A/MTCLKA-A/TMRI1/SCK3-B/USB0_VBUSEN-A Figure 1.5 Pin Assignment of the 144-Pin LQFP R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 P22/EDREQ0-B/PO2/MTIOC3B-A/MTCLKC-A/TMO0/SCK0/USB0_DRPD P23/EDACK0-B/PO3/MTIOC3D-A/MTCLKD-A/TxD3-B/USB0_DPUPE-A P21/PO1/MTIOC1B/TMCI0-B/RxD0/SCL1/USB0_EXICEN P33/PO11/MTIOC0D/RxD6-B/CRX0/IRQ3-A P32/PO10/MTIOC0C/TxD6-B/CTX0/IRQ2-A/RTCOUT P34/PO12/MTIOC0A/TMCI3/SCK6-B/IRQ4-A/TRST# P31/PO9/MTIOC4D-A/TMCI2-B/SSLB0-A/IRQ1/TMS VSS P02/TMCI1-A/SCK6-A/IRQ10-A WDTOVF# AVSS P01/TMCI0-A/RxD6-A/IRQ9-A P00/TMRI0-A/TxD6-A/IRQ8-A VSS MDE VCL MD1 BSCANP EMLE MD0 XTAL VSS P05/DA1/IRQ13-A P03/DA0/IRQ11-A EXTAL P35/NMI P30/PO8/MTIOC4B-A/TMRI3/RxD1/MISOB-A/IRQ0/TDI 36 144 1 2 3 4 5 6 7 8 9 37 Page 12 of 146 RX62N Group, RX621 Group 1. Overview 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PC1/A17-A/MTCLKH-A/SCK5/SSLA2-A/ET_ERXD2 72 71 70 69 68 67 PC0/A16-A/MTCLKG-A/SSLA1-A/ET_ERXD3 VCC PA0/A0/BC0#/PO16/MTIOC6A/SSLA1-B PB4/A12/PO28/MTIOC10A/MTCLKE-B PB5/A13/PO29/MTIOC10C/MTCLKF-B PB2/A10/PO26/MTIOC9B/MTCLKG-B PB3/A11/PO27/MTIOC9D/MTCLKH-B PA5/A5/PO21/MTIOC7B/RSPCKA-B PA6/A6/PO22/MTIOC8A/MOSIA-B PA7/A7/PO23/MTIOC8B/MISOA-B PA1/A1/PO17/MTIOC6B/SSLA2-B PA2/A2/PO18/MTIOC6C/SSLA3-B PA4/A4/PO20/MTIOC7A/SSLA0-B VCC PE5/D13/RSPCKB-B/IRQ5-A VSS PE6/D14/MOSIB-B/IRQ6-A PE7/D15/MISOB-B/IRQ7-A PB6/A14/PO30/MTIOC10B PB7/A15/PO31/MTIOC10D PA3/A3/PO19/MTIOC6D VSS P72/CS2#-B/ET_MDC PB1/A9/PO25/MTIOC9C PB0/A8/PO24/MTIOC9A P71/CS1#-B/ET_MDIO P73/CS3#-B/ET_WOL P66/CS6#-A/DQM0 P67/CS7#-A/DQM1 PE4/D12/SSLB0-B P65/CS5#-A/CKE PE3/D11/POE8# P70/SDCLK VCC VSS P74/CS4#-B/ET_ERXD1/RMII_RXD1 P75/CS5#-B/ET_ERXD0/RMII_RXD0 PC2/A18-A/MTCLKE-A/RxD5/SSLA3-A/ET_RX_DV P76/CS6#-B/ET_RX_CLK/REF50CK P77/CS7#-B/ET_RX_ER/RMII_RX_ER PC3/A19-A/MTCLKF-A/TxD5/ET_TX_ER PC4/A20/CS3#-C/MTCLKC-B/SSLA0-A/ET_TX_CLK P80/EDREQ0-A/MTIOC3B-B/ET_TX_EN/RMII_TXD_EN/TRDATA0 P81/EDACK0-A/MTIOC3D-B/ET_ETXD0/RMII_TXD0/TRDATA1 P82/EDREQ1-A/MTIOC4A-B/ET_ETXD1/RMII_TXD1/TRSYNC PC5/A21/CS2#-C/WAIT#-C/MTIC11W-A/MTCLKD-B/RSPCKA-A/ET_ETXD2 PC6/A22/CS1#-C/MTIC11V-A/MTCLKA-B/MOSIA-A/ET_ETXD3 PC7/A23/CS0#-B/MTIC11U-A/MTCLKB-B/MISOA-A/ET_COL VCC P83/EDACK1-A/MTIOC4C-B/ET_CRS/RMII_CRS_DV/TRCLK VSS P50/WR0#/WR#/TxD2-B/SSLB1-A P51/WR1#/BC1#/WAIT#-D/SCK2/SSLB2-A P52/RD#/RxD2-B/SSLB3-A P53/BCLK P54/EDACK0-C/MTIOC4B-B/ET_LINKSTA/TRDATA2 P55/WAIT#-B/EDREQ0-C/MTIOC4D-B/ET_EXOUT/TRDATA3 P56/EDACK1-C/MTIOC3C-B VSS_USB USB0_DP USB0_DM VCC_USB P12/TMCI1-B/RxD2-A/SCL0/IRQ2-B P13/ADTRG1#/TMO3/TxD2-A/SDA0/IRQ3-B P14/TMRI2/IRQ4-B/USB0_OVRCURA/USB0_DPUPE-B P15/PO13/MTIOC0B/TMCI2-A/SCK3-A/IRQ5-B PLLVSS P16/PO14/MTIOC3C-A/TMO2/RxD3-A/IRQ6-B/USB0_VBUS/USB0_OVRCURB/USB0_VBUSEN-B PLLVCC P17/PO15/MTIOC3A/TxD3-A/IRQ7-B P20/PO0/MTIOC1A/TMRI0-B/TxD0/SDA1/USB0_ID PE2/D10/SSLB3-B/POE9# PE1/D9/SSLB2-B PE0/D8/SSLB1-B P64/CS4#-A/WE# P63/CS3#-A/CAS# P62/CS2#-A/RAS# P61/CS1#-A/SDCS# VSS P60/CS0#-A VCC PD7/D7/MTIC5U/POE0# PD6/D6/MTIC5V/POE1# PD5/D5/MTIC5W/POE2# PD4/D4/MTIC11U-B/POE3# PD3/D3/MTIC11V-B/POE4# PD2/D2/MTIC11W-B/POE5# PD1/D1/POE6# PD0/D0/POE7# P93/A19-B P92/A18-B P91/A17-B VSS P90/A16-B VCC P47/AN7/IRQ15-B P46/AN6/IRQ14 P45/AN5/IRQ13-B P44/AN4/IRQ12 P43/AN3/IRQ11-B P42/AN2/IRQ10-B P41/AN1/IRQ9-B VREFL P40/AN0/IRQ8-B VREFH AVCC P07/ADTRG0#-A/IRQ15-A 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 66 65 64 63 62 61 60 59 58 57 RX62N Group RX621 Group PLQP0144KA-A (144-pin LQFP) (Top view) 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 25 26 27 28 29 30 31 32 33 34 35 P05/DA1/IRQ13-A VSS P02/TMCI1-A/SCK6-A/IRQ10-A P03/DA0/IRQ11-A P01/TMCI0-A/RxD6-A/IRQ9-A P00/TMRI0-A/TxD6-A/IRQ8-A EXTAL MDE VCL MD1 RES# MD0 XTAL P34/PO12/MTIOC0A/TMCI3/SCK6-B/IRQ4-A/TRST# P33/PO11/MTIOC0D/RxD6-B/CRX0/IRQ3-A P31/PO9/MTIOC4D-A/TMCI2-B/SSLB0-A/IRQ1/TMS WDTOVF# BSCANP EMLE XCOUT AVSS VSS VSS P27/CS7#-C/PO7/MTIOC2B/SCK1/RSPCKB-A/TCK P26/CS6#-C/PO6/MTIOC2A/TMO1/TxD1/MOSIB-A/TDO P25/CS5#-C/EDACK1-B/ADTRG0#-B/PO5/MTIOC4C-A/MTCLKB-A/RxD3-B/USB0_DPRPD P24/CS4#-C/EDREQ1-B/PO4/MTIOC4A-A/MTCLKA-A/TMRI1/SCK3-B/USB0_VBUSEN-A P23/EDACK0-B/PO3/MTIOC3D-A/MTCLKD-A/TxD3-B/USB0_DPUPE-A P32/PO10/MTIOC0C/TxD6-B/CTX0/IRQ2-A/RTCOUT P30/PO8/MTIOC4B-A/TMRI3/RxD1/MISOB-A/IRQ0/TDI P35/NMI XCIN VCC P22/EDREQ0-B/PO2/MTIOC3B-A/MTCLKC-A/TMO0/SCK0/USB0_DRPD VCC Figure 1.6 Pin Assignment of the 144-Pin LQFP (Assistance Diagram) R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 P21/PO1/MTIOC1B/TMCI0-B/RxD0/SCL1/USB0_EXICEN 36 144 1 2 3 4 5 6 7 8 9 Page 13 of 146 RX62N Group, RX621 Group 1. Overview PB4/A12/PO28/MTIOC10A/MTCLKE-B/ET_TX_EN/RMII_TXD_EN PB3/A11/PO27/MTIOC9D/MTCLKH-B/ET_RX_ER/RMII_RX_ER PB5/A13/PO29/MTIOC10C/MTCLKF-B/ET_ETXD0/RMII_TXD0 PB2/A10/PO26/MTIOC9B/MTCLKG-B/ET_RX_CLK/REF50CK PB7/A15/PO31/MTIOC10D/ET_CRS/RMII_CRS_DV 53 PB6/A14/PO30/MTIOC10B/ET_ETXD1/RMII_TXD1 PA5/A5/PO21/MTIOC7B/RSPCKA-B/ET_LINKSTA 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 52 PE2/D10/SSLB3-B/POE9# PE1/D9/SSLB2-B PE0/D8/SSLB1-B PD7/D7/MTIC5U/POE0# PD6/D6/MTIC5V/POE1# PD5/D5/MTIC5W/POE2# PD4/D4/MTIC11U-B/POE3# PD3/D3/MTIC11V-B/POE4# PD2/D2/MTIC11W-B/POE5# PD1/D1/POE6# PD0/D0/POE7# P47/AN7/IRQ15-B P46/AN6/IRQ14 P45/AN5/IRQ13-B P44/AN4/IRQ12 P43/AN3/IRQ11 P42/AN2/IRQ10 P41/AN1/IRQ9 VREFL P40/AN0/IRQ8 VREFH AVCC P07/ADTRG0#-A/IRQ15-A AVSS P05/DA1/IRQ13-A 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 51 PC1/A17/MTCLKH-A/SCK5/SSLA2-A/ET_ERXD2 PB1/A9/PO25/MTIOC9C/ET_ERXD0/RMII_RXD0 PB0/A8/PO24/MTIOC9A/ET_ERXD1/RMII_RXD1 PA6/A6/PO22/MTIOC8A/MOSIA-B/ET_EXOUT PA7/A7/PO23/MTIOC8B/MISOA-B/ET_WOL PA4/A4/PO20/MTIOC7A/SSLA0-B/ET_MDC PC0/A16/MTCLKG-A/SSLA1-A/ET_ERXD3 PA0/A0/BC0#/PO16/MTIOC6A/SSLA1-B PA3/A3/PO19/MTIOC6D/ET_MDIO PA2/A2/PO18/MTIOC6C/SSLA3-B PA1/A1/PO17/MTIOC6B/SSLA2-B PE6/D14/MOSIB-B/IRQ6-A PE5/D13/RSPCKB-B/IRQ5 PE7/D15/MISOB-B/IRQ7 PE4/D12/SSLB0-B PE3/D11/POE8# VCC VSS 50 49 48 47 46 45 44 43 PC2/A18/MTCLKE-A/RxD5/SSLA3-A/ET_RX_DV PC3/A19/MTCLKF-A/TxD5/ET_TX_ER PC4/A20/CS3#/MTCLKC-B/SSLA0-A/ET_TX_CLK PC5/A21/CS2#/WAIT#-C/MTIC11W-A/MTCLKD-B/RSPCKA-A/ET_ETXD2 PC6/A22/CS1#/MTIC11V-A/MTCLKA-B/MOSIA-A/ET_ETXD3 PC7/A23/CS0#/MTIC11U-A/MTCLKB-B/MISOA-A/ET_COL P50/WR0#/WR#/TxD2-B/SSLB1-A P51/WR1#/BC1#/WAIT#-D/SCK2/SSLB2-A P52/RD#/RxD2-B/SSLB3-A P53/BCLK P54/MTIOC4B-B P55/WAIT#-B/MTIOC4D-B VSS_USB USB0_DP USB0_DM VCC_USB P12/TMCI1/RxD2-A/SCL0/IRQ2-B P13/ADTRG1#/PO13/MTIOC0B/TMO3/TxD2-A/SDA0/IRQ3-B P14/PO15/MTIOC3A/TMRI2/IRQ4-B/USB0_OVRCURA/USB0_DPUPE-B PLLVSS P16/PO14/MTIOC3C/TMO2/IRQ6-B/USB0_VBUS/USB0_OVRCURB/USB0_VBUSEN-B PLLVCC P20/PO0/MTIOC1A/TMRI0/TxD0/USB0_ID P21/PO1/MTIOC1B/TMCI0/RxD0/USB0_EXICEN P22/PO2/MTIOC3B/MTCLKC-A/TMO0/SCK0/USB0_DRPD RX62N Group RX621 Group PLQP0100KB-A (100-pin LQFP) (Top view) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VCC XCIN VCC P25/CS5#/ADTRG0#-B/PO5/MTIOC4C/MTCLKB-A/RxD3/USB0_DPRPD P30/PO8/MTIOC4B-A/TMRI3/RxD1/MISOB-A/IRQ0/TDI P35/NMI P24/CS4#/PO4/MTIOC4A/MTCLKA-A/TMRI1/SCK3/USB0_VBUSEN-A P26/CS6#/PO6/MTIOC2A/TMO1/TxD1/MOSIB-A/TDO P27/CS7#/PO7/MTIOC2B/SCK1/RSPCKB-A/TCK VSS EMLE MDE VSS Figure 1.7 Pin Assignment of the 100-Pin LQFP R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 P23/PO3/MTIOC3D/MTCLKD-A/TxD3/USB0_DPUPE-A P34/PO12/MTIOC0A/TMCI3/SCK6/IRQ4-A/TRST# P33/PO11/MTIOC0D/RxD6/CRX0/IRQ3-A XCOUT RES# XTAL EXTAL VCL MD1 MD0 P32/PO10/MTIOC0C/TxD6/CTX0/IRQ2-A/RTCOUT P31/PO9/MTIOC4D-A/TMCI2/SSLB0-A/IRQ1/TMS Page 14 of 146 RX62N Group, RX621 Group 1. Overview PB4/A12/PO28/MTIOC10A/MTCLKE-B/ET_TX_EN/RMII_TXD_EN PB3/A11/PO27/MTIOC9D/MTCLKH-B/ET_RX_ER/RMII_RX_ER PB5/A13/PO29/MTIOC10C/MTCLKF-B/ET_ETXD0/RMII_TXD0 PB2/A10/PO26/MTIOC9B/MTCLKG-B/ET_RX_CLK/REF50CK PB7/A15/PO31/MTIOC10D/ET_CRS/RMII_CRS_DV 53 PB6/A14/PO30/MTIOC10B/ET_ETXD1/RMII_TXD1 PA5/A5/PO21/MTIOC7B/RSPCKA-B/ET_LINKSTA 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 52 51 50 49 48 47 46 45 PC1/A17/MTCLKH-A/SCK5/SSLA2-A/ET_ERXD2 PB1/A9/PO25/MTIOC9C/ET_ERXD0/RMII_RXD0 PB0/A8/PO24/MTIOC9A/ET_ERXD1/RMII_RXD1 PA6/A6/PO22/MTIOC8A/MOSIA-B/ET_EXOUT PA7/A7/PO23/MTIOC8B/MISOA-B/ET_WOL PA4/A4/PO20/MTIOC7A/SSLA0-B/ET_MDC PC0/A16/MTCLKG-A/SSLA1-A/ET_ERXD3 PA0/A0/BC0#/PO16/TIOC6A/SSLA1-B PA3/A3/PO19/MTIOC6D/ET_MDIO PA2/A2/PO18/MTIOC6C/SSLA3-B PA1/A1/PO17/MTIOC6B/SSLA2-B PE6/D14/MOSIB-B/IRQ6-A PE5/D13/RSPCKB-B/IRQ5 PE7/D15/MISOB-B/IRQ7 PE4/D12/SSLB0-B PE3/D11/POE8# VCC VSS PC2/A18/MTCLKE-A/RxD5/SSLA3-A/ET_RX_DV PC3/A19/MTCLKF-A/TxD5/ET_TX_ER PC4/A20/CS3#/MTCLKC-B/SSLA0-A/ET_TX_CLK PC5/A21/CS2#/WAIT#-C/MTIC11W-A/MTCLKD-B/RSPCKA-A/ET_ETXD2 PC6/A22/CS1#/MTIC11V-A/MTCLKA-B/MOSIA-A/ET_ETXD3 PC7/A23/CS0#/MTIC11U-A/MTCLKB-B/MISOA-A/ET_COL P50/WR0#/WR#/TxD2-B/SSLB1-A P51/WR1#/BC1#/WAIT#-D/SCK2/SSLB2-A P52/RD#/RxD2-B/SSLB3-A P53/BCLK P54/MTIOC4B-B P55/WAIT#-B/MTIOC4D-B VSS_USB USB0_DP USB0_DM VCC_USB P12/TMCI1/RxD2-A/SCL0/IRQ2-B P13/ADTRG1#/PO13/MTIOC0B/TMO3/TxD2-A/SDA0/IRQ3-B P14/PO15/MTIOC3A/TMRI2/IRQ4-B/USB0_OVRCURA/USB0_DPUPE-B PLLVSS P16/PO14/MTIOC3C/TMO2/IRQ6-B/USB0_VBUS/USB0_OVRCURB/USB0_VBUSEN-B PLLVCC P20/PO0/MTIOC1A/TMRI0/TxD0/USB0_ID P21/PO1/MTIOC1B/TMCI0/RxD0/USB0_EXICEN P22/PO2/MTIOC3B/MTCLKC-A/TMO0/SCK0/USB0_DRPD PE2/D10/SSLB3-B/POE9# PE1/D9/SSLB2-B PE0/D8/SSLB1-B PD7/D7/MTIC5U/POE0# PD6/D6/MTIC5V/POE1# PD5/D5/MTIC5W/POE2# PD4/D4/MTIC11U-B/POE3# PD3/D3/MTIC11V-B/POE4# PD2/D2/MTIC11W-B/POE5# PD1/D1/POE6# PD0/D0/POE7# P47/AN7/IRQ15-B P46/AN6/IRQ14 P45/AN5/IRQ13-B P44/AN4/IRQ12 P43/AN3/IRQ11 P42/AN2/IRQ10 P41/AN1/IRQ9 VREFL P40/AN0/IRQ8 VREFH AVCC P07/ADTRG0#-A/IRQ15-A AVSS P05/DA1/IRQ13-A 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 11 12 13 14 15 16 17 44 43 42 41 40 RX62N Group RX621 Group PLQP0100KB-A (100-pin LQFP) (Top view) 39 38 37 36 35 34 33 32 31 30 29 28 27 26 18 19 20 21 22 23 24 XCOUT P32/PO10/MTIOC0C/TxD6/CTX0/IRQ2-A/RTCOUT P30/PO8/MTIOC4B-A/TMRI3/RxD1/MISOB-A/IRQ0/TDI P27/CS7#/PO7/MTIOC2B/SCK1/RSPCKB-A/TCK VSS Figure 1.8 Pin Assignment of the 100-Pin LQFP (Assistance Diagram) R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 P25/CS5#/ADTRG0#-B/PO5/MTIOC4C/MTCLKB-A/RxD3/USB0_DPRPD P24/CS4#/PO4/MTIOC4A/MTCLKA-A/TMRI1/SCK3/USB0_VBUSEN-A P23/PO3/MTIOC3D/MTCLKD-A/TxD3/USB0_DPUPE-A P33/PO11/MTIOC0D/RxD6/CRX0/IRQ3-A P26/CS6#/PO6/MTIOC2A/TMO1/TxD1/MOSIB-A/TDO EMLE VSS MDE EXTAL RES# XTAL VCL MD1 MD0 P35/NMI P34/PO12/MTIOC0A/TMCI3/SCK6/IRQ4-A/TRST# P31/PO9/MTIOC4D-A/TMCI2/SSLB0-A/IRQ1/TMS XCIN VCC VCC 25 1 2 3 4 5 6 7 8 9 Page 15 of 146 RX62N Group, RX621 Group 1. Overview A 10 PD6 B PA1 C PA0 D PA2 E PA4 F PA7 G PB1 H PB4 J PC0 K PC1 10 9 PD7 PA3 PA5 PA6 PB0 PB2 PB5 PB7 PC3 PC2 9 8 PD5 PD3 BSCANP VCL VSS VCC PB3 PB6 P51 P50 8 7 PD4 PD2 MD1 P53 P52 VSS_ USB USB0_ DP 7 6 PD1 PD0 P45 5 P47 P46 P44 RX62N Group RX621 Group PTLG0085JA-A (85-pin TFLGA) (Upper perspective view) RES# P13 USB0_ DM VCC_ USB 6 P14 P12 5 4 P43 P42 P41 PLLVCC P16 PLLVSS 4 3 VREFL VREFH P40 MD0 P34 P32 P27 P26 P24 P20 3 2 AVCC AVSS VSS EMLE XCOUT EXTAL P33 P30 P23 P22 2 1 P05 VCC P03 MDE XCIN XTAL P35 P31 P25 P21 1 A B C D E F G H J K Figure 1.9 Pin Assignment of the 85-Pin TFLGA R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 16 of 146 RX62N Group, RX621 Group 1. Overview Table 1.4 Pin No. 176-Pin LFBGA List of Pins and Pin Functions (176-Pin LFBGA) (1 / 6) Power Supply Clock System Control External Bus EXDMAC Timers (MTU, TMR, PPG, POE, WDT) Communication (SCI, CAN, RSPI, RIIC) I/O Port ETHERC EDMAC USB Others A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 C1 C2 C3 C4 C5 AVSS AVCC P42 P45 P46 P90 PD0 PD2 PD3 PD4 PG0 PD7 P61 P63 PE1 P02 VREFH VREFL P44 P47 P91 PD1 P96 P97 PD6 P60 P62 P64 PE2 SDCLK P70 P00 P03 P05 P07 P40 TMRI0-A TxD6-A IRQ8-A IRQ11-A/DA0 IRQ13-A/DA1 IRQ15-A/ ADTRG0#-A IRQ8-B/AN0 D17/A17-B D1 D22/A22-B D23/A23-B D6 CS0#-A CS2#-A/ RAS# CS4#-A/ WE# D10 POE9# SSLB3-B MTIC5V-B/ POE1# POE6# IRQ12/AN4 IRQ15-B/AN7 D16/A16-B D0 D2 D3 D4 D24 D7 CS1#-A/ SDCS# CS3#-A/ CAS# D9 TMCI1-A SSLB2-B SCK6-A IRQ10-A MTIC5U-B/ POE0# POE7# MTIC11W-B/ POE5# MTIC11V-B/ POE4# MTIC11U-B/ POE3# IRQ10-B/AN2 IRQ13-B/AN5 IRQ14/AN6 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 17 of 146 RX62N Group, RX621 Group Table 1.4 Pin No. 176-Pin LFBGA 1. Overview List of Pins and Pin Functions (176-Pin LFBGA) (2 / 6) Power Supply Clock System Control External Bus EXDMAC Timers (MTU, TMR, PPG, POE, WDT) Communication (SCI, CAN, RSPI, RIIC) I/O Port ETHERC EDMAC USB Others C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 E1 E2 E3 E4 E12 E13 E14 E15 F1 F2 F3 F4 F12 F13 F14 VCC P92 P94 VCC PD5 VCC PE0 PE3 PE5 PE6 EMLE P01 VCC P41 P43 VSS P93 P95 VSS PG1 VSS VSS PE4 PE7 P65 XCIN CNVSS BSCANP VSS PG2 VCC P66 P67 XCOUT WDTOVF# VCL VSS PG4 PG3 PA0 D28 D27 A0/BC0#/ DQM2 MTIOC6A/ PO16 SSLA1-B TRSYNC TRDATA1 CS6#-A/ DQM0 CS7#-A/ DQM1 D26 TRDATA0 D12 D15 CS5#-A/ CKE SSLB0-B MISOB-B IRQ7-A D25 D19/A19-B D21/A21-B IRQ9-B/AN1 IRQ11-B/AN3 TMCI0-A RxD6-A IRQ9-A D8 D11 D13 D14 POE8# RSPCKB-B MOSIB-B IRQ5-A IRQ6-A SSLB1-B D5 MTIC5W-B/ POE2# D18/A18-B D20/A20-B R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 18 of 146 RX62N Group, RX621 Group Table 1.4 Pin No. 176-Pin LFBGA 1. Overview List of Pins and Pin Functions (176-Pin LFBGA) (3 / 6) Power Supply Clock System Control External Bus EXDMAC Timers (MTU, TMR, PPG, POE, WDT) Communication (SCI, CAN, RSPI, RIIC) I/O Port ETHERC EDMAC USB Others F15 G1 G2 G3 G4 G12 G13 G14 G15 H1 H2 H3 H4 H12 H13 H14 H15 J1 J2 EXTAL VCC RES# XTAL VSS MD1 MD0 MDE VSS VCC PG5 D29 TRCLK PG6 PA1 D30 A1/DQM3 MTIOC6B/ PO17 SSLA2-B TRDATA2 P35 NMI PG7 PA2 PA4 PA3 D31 A2 A4 A3 MTIOC6C/ PO18 MTIOC7A/ PO20 MTIOC6D/ PO19 SSLA3-B SSLA0-B TRDATA3 P32 MTIOC0C/ PO10/ RTCOUT CTX0/ TxD6-B IRQ2-A J3 J4 PF3 P34 MTIOC0A/ TMCI3-B/ PO12 SCK6-B TMS IRQ4-A J12 J13 J14 J15 K1 K2 VSS PA5 PA7 PA6 P33 P31 USB1_DPRPD A5 A7 A6 MTIOC7B/ PO21 MTIOC8B/ PO23 MTIOC8A/ PO22 MTIOC0D/ PO11 MTIOC4D-A/ TMCI2-B/ PO9 RSPCKA-B MISOA-B MOSIA-B CRX0/ RxD6-B SSLB0-A IRQ3-A IRQ1-A K3 K4 K12 K13 K14 PF0 PF4 PB1 P71 P72 A9 CS1#-B CS2#-B ET_MDIO ET_MDC MTIOC9C/ PO25 TxD1-B TDO TRST# R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 19 of 146 RX62N Group, RX621 Group Table 1.4 Pin No. 176-Pin LFBGA 1. Overview List of Pins and Pin Functions (176-Pin LFBGA) (4 / 6) Power Supply Clock System Control External Bus EXDMAC Timers (MTU, TMR, PPG, POE, WDT) Communication (SCI, CAN, RSPI, RIIC) I/O Port ETHERC EDMAC USB Others K15 L1 L2 L3 L4 VCC PB0 PF2 P27 A8 MTIOC9A/ PO24 RxD1-B TDI CS7#-C USB1_EXICEN MTIOC2B/ PO7 RSPCKB-A/ SCK1-A P30 USB1_DRPD MTIOC4B-A/ TMRI3-B/ PO8 MISOB-A/ RxD1-A IRQ0-A L12 L13 VSS PB4 A12 MTIOC10A/ MTCLKE-B/ PO28 MTIOC9D/ MTCLKH-B/ PO27 L14 PB3 A11 L15 M1 M2 VCC PF1 P25 CS5#-C/ EDACK1-B EDREQ0-B USB0_DPRPD MTIOC4C-A/ MTCLKB-A/ PO5 MTIOC3B-A/ MTCLKC-A/ TMO0/ PO2 SCK1-B RxD3-B TCK ADTRG0#-B M3 P22 USB0_DRPD SCK0 M4 M5 M6 M7 M8 VSS P11 P55 P54 P51 WAIT#-B/ EDREQ0-C EDACK0-C WR1#/ BC1#/ WAIT#-D ET_EXOUT ET_LINKSTA USB1_VBUSEN -A MTIC5V-A/ TMCI3-A MTIOC4D-B MTIOC4B-B SSLB2-A/ SCK2-B SCK2-A IRQ1-B M9 M10 M11 M12 M13 M14 M15 VSS PC6 P81 PC0 VCC PB6 PB2 A14 A10 MTIOC10B/ PO30 MTIOC9B/ MTCLKG-B/ PO26 USB1_ID MTIOC2A/ TMO1/ PO6 MOSIB-A/ TxD1-A A22-A/ CS1#-C EDACK0-A A16-A ET_ETXD3 ET_ETXD0/ RMII_TXD0 ET_ERXD3 MTIC11V-A/ MTCLKA-B MTIOC3D-B MTCLKG-A SSLA1-A MOSIA-A N1 P26 CS6#-C R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 20 of 146 RX62N Group, RX621 Group Table 1.4 Pin No. 176-Pin LFBGA 1. Overview List of Pins and Pin Functions (176-Pin LFBGA) (5 / 6) Power Supply Clock System Control External Bus EXDMAC Timers (MTU, TMR, PPG, POE, WDT) Communication (SCI, CAN, RSPI, RIIC) I/O Port ETHERC EDMAC USB Others N2 P23 EDACK0-B USB0_DPUPEA USB0_ID MTIOC3D-A/ MTCLKD-A/ PO3 MTIOC1A/ TMRI0-B/ PO0 MTIOC3A/ PO15 TxD3-B N3 P20 SDA1/ TxD0 TxD3-A IRQ7-B N4 P17 USB1_VBUS/ USB1_OVRCU RB/ USB1_VBUSEN -B USB1_OVRCU RA/ USB1_DPUPEB WAIT#-A/ WR3#/ BC3#/ EDREQ1-C USB1_DPUPEA RD# N5 P15 MTIOC0B/ TMCI2-A/ PO13 SCK3-A IRQ5-B N6 P57 N7 N8 N9 N10 VCC P10 P52 MTIC5W-A/ TMRI3-A SSLB3-A/ RxD2-B IRQ0-B PC5 A21-A/ CS2#-C/ WAIT#-C A19-A A18-A CS4#-B CS3#-B A13 ET_ETXD2 MTIC11W-A/ MTCLKD-B MTCLKF-A MTCLKE-A RSPCKA-A N11 N12 N13 N14 N15 PC3 PC2 P74 P73 PB5 ET_TX_ER ET_RX_DV ET_ERXD1/ RMII_RXD1 ET_WOL TxD5 SSLA3-A/ RxD5 MTIOC10C/ MTCLKF-B/ PO29 USB0_VBUSEN -A MTIOC4A-A/ MTCLKA-A/ TMRI1/ PO4 SCK3-B P1 P24 CS4#-C/ EDREQ1-B P2 P3 PLLVCC P16 USB0_VBUS/ USB0_OVRCU RB/ USB0_VBUSEN -B USB0_OVRCU RA/ USB0_DPUPEB MTIOC3C-A/ TMO2/ PO14 RxD3-A IRQ6-B P4 P14 TMRI2 IRQ4-B P5 P6 VCC_USB P13 TMO3 SDA0/ TxD2-A IRQ3-B/ ADTRG1# R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 21 of 146 RX62N Group, RX621 Group Table 1.4 Pin No. 176-Pin LFBGA 1. Overview List of Pins and Pin Functions (176-Pin LFBGA) (6 / 6) Power Supply Clock System Control External Bus EXDMAC Timers (MTU, TMR, PPG, POE, WDT) Communication (SCI, CAN, RSPI, RIIC) I/O Port ETHERC EDMAC USB Others P7 P56 WR2#/ BC2#/ EDACK1-C MTIOC3C-B P8 P9 P10 P11 P12 P13 P14 P15 R1 VCC_USB P84 P50 P82 PC4 P76 PC1 PB7 P21 WR0#/ WR# EDREQ1-A A20-A/ CS3#-C CS6#-B A17-A A15 USB0_EXICEN ET_ETXD1/ RMII_TXD1 ET_TX_CLK ET_RX_CLK/ REF50CK ET_ERXD2 MTCLKH-A MTIOC10D/ PO31 MTIOC1B/ TMCI0-B/ PO1 SCL1/ RxD0 SSLA2-A/ SCK5 MTIOC4A-B MTCLKC-B SSLA0-A SSLB1-A/ TxD2-B R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 PLLVSS P12 USB0_DM USB0_DP VSS_USB USB1_DM USB1_DP P85 BCLK P53 P83 EDACK1-A ET_CRS/ RMII_CRS_D V ET_COL ET_TX_EN/ RMII_TXD_E N ET_RX_ER/ RMII_RX_ER ET_ERXD0/ RMII_RXD0 MTIOC4C-B MTIC5U-A/ TMCI1-B SCL0/ RxD2-A IRQ2-B R12 R13 PC7 P80 A23-A/ CS0#-B EDREQ0-A MTIC11U-A/ MTCLKB-B MTIOC3B-B MISOA-A R14 R15 P77 P75 CS7#-B CS5#-B R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 22 of 146 RX62N Group, RX621 Group 1. Overview Table 1.5 Pin No. 145-Pin TFLGA List of Pins and Pin Functions (145-Pin TFLGA) (1 / 5) Power Supply Clock System Control Timers (MTU, TMR, PPG, POE, WDT) Communication (SCI, CAN, RSPI, RIIC) I/O Port External Bus EXDMAC ETHERC EDMAC USB Others A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 C3 C4 C5 C6 C7 C8 C9 AVSS AVCC VREFL P42 P44 P47 P91 PD0 PD3 PD6 P60 P62 P64 P03 P07 VREFH P40 P45 P90 PD1 PD5 VSS PE0 PE2 PE1 PE4 P01 P05 VSS P41 P46 P92 PD2 PD7 P61 A18-B D2 D7 CS1#-A/ SDCS# MTIC11W-B/ POE5# MTIC5U/ POE0# IRQ9-B/AN1 IRQ14/AN6 D8 D10 D9 D12 TMCI0-A POE9# SSLB1-B SSLB3-B SSLB2-B SSLB0-B RxD6-A IRQ9-A IRQ13-A/DA1 A16-B D1 D5 POE6# MTIC5W/ POE2# IRQ8-B/AN0 IRQ13-B/AN5 A17-B D0 D3 D6 CS0#-A CS2#-A/ RAS# CS4#-A/ WE# IRQ11-A/DA0 IRQ15-A/ ADTRG0#-A POE7# MTIC11V-B/ POE4# MTIC5V/ POE1# IRQ10-B/AN2 IRQ12/AN4 IRQ15-B/AN7 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 23 of 146 RX62N Group, RX621 Group Table 1.5 Pin No. 145-Pin TFLGA 1. Overview List of Pins and Pin Functions (145-Pin TFLGA) (2 / 5) Power Supply Clock System Control Timers (MTU, TMR, PPG, POE, WDT) Communication (SCI, CAN, RSPI, RIIC) I/O Port External Bus EXDMAC ETHERC EDMAC USB Others C10 P63 PE5 CS3#-A/ CAS# D13 D11 POE8# RSPCKB-B IRQ5-A C11 C12 C13 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 E1 E2 E3 E4 E5 E10 E11 E12 E13 F1 F2 F3 F4 F10 F11 F12 F13 G1 G2 XTAL VSS VCC PA2 A2 MTIOC6C/ PO18 SSLA3-B MDE PA1 PA3 A1 A3 MTIOC6B/ PO17 MTIOC6D/ PO19 SSLA2-B XCIN XCOUT WDTOVF# BSCANP AiN.CAj P65 P67 PA0 P66 CS5#-A/ CKE CS7#-A/ DQM1 A0/BC0# CS6#-A/ DQM0 MTIOC6A/ PO16 SSLA1-B VCL VSS P00 TMRI0-A TxD6-A IRQ8-A VCC VSS VCC PE7 PE6 D15 D14 MISOB-B MOSIB-B IRQ7-A IRQ6-A VCC VSS P93 PD4 A19-B D4 MTIC11U-B/ POE3# SDCLK EMLE VCC P02 P43 TMCI1-A SCK6-A IRQ10-A IRQ11-B/AN3 PE3 P70 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 24 of 146 RX62N Group, RX621 Group Table 1.5 Pin No. 145-Pin TFLGA 1. Overview List of Pins and Pin Functions (145-Pin TFLGA) (3 / 5) Power Supply Clock System Control Timers (MTU, TMR, PPG, POE, WDT) Communication (SCI, CAN, RSPI, RIIC) I/O Port External Bus EXDMAC ETHERC EDMAC USB Others G3 G4 G10 G11 G12 G13 H1 H2 MD1 MD0 VSS PA5 PA6 PA4 EXTAL P34 MTIOC0A/ TMCI3/ PO12 SCK6-B IRQ4-A/ TRST# A5 A6 A4 MTIOC7B/ PO21 MTIOC8A/ PO22 MTIOC7A/ PO20 RSPCKA-B MOSIA-B SSLA0-B H3 H4 H10 H11 H12 H13 J1 J2 J3 J4 VCC RES# PB0 P71 PB1 PA7 P33 P27 P35 P32 MTIOC0C/ PO10/ RTCOUT A10 MTIOC9B/ MTCLKG-B/ PO26 MTIOC10A/ MTCLKE-B/ PO28 MTIOC10C/ MTCLKF-B/ PO29 ET_MDC MTIOC4B-A/ TMRI3/ PO8 CS4#-C/ EDREQ1-B USB0_VBUSE N-A MTIOC4A-A/ MTCLKA-A/ TMRI1/PO4 MTIOC4D-A/ TMCI2-B/ PO9 RxD1/ MISOB-A SCK3-B IRQ0/ TDI CTX0/ TxD6-B CS7#-C A8 CS1#-B A9 A7 ET_MDIO MTIOC9C/ PO25 MTIOC8B/ PO23 MTIOC0D/ PO11 MTIOC2B/ PO7 MISOA-B CRX0/ RxD6-B RSPCKB-A/ SCK1 IRQ3-A TCK NMI IRQ2-A MTIOC9A/ PO24 J10 PB2 J11 PB4 A12 J12 PB5 A13 J13 K1 P72 P30 CS2#-B K2 P24 K3 P31 SSLB0-A IRQ1/ TMS R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 25 of 146 RX62N Group, RX621 Group Table 1.5 Pin No. 145-Pin TFLGA 1. Overview List of Pins and Pin Functions (145-Pin TFLGA) (4 / 5) Power Supply Clock System Control Timers (MTU, TMR, PPG, POE, WDT) Communication (SCI, CAN, RSPI, RIIC) I/O Port External Bus EXDMAC ETHERC EDMAC USB Others K4 P26 CS6#-C MTIOC2A/ TMO1/ PO6 MOSIB-A/ TxD1 TDO K5 K6 K7 K8 K9 K10 K11 K12 K13 BCLK VSS P53 PC7 P82 PC3 PB7 P73 PC0 PB3 A23/ CS0#-B EDREQ1-A A19-A A15 CS3#-B A16-A A11 ET_COL ET_ETXD1/ RMII_TXD1 ET_TX_ER MTIC11U-A/ MTCLKB-B MTIOC4A-B MTCLKF-A MTIOC10D/ PO31 MISOA-A TRSYNC TxD5 ET_WOL ET_ERXD3 MTCLKG-A MTIOC9D/ MTCLKH-B/ PO27 USB0_DPRPD MTIOC4C-A/ MTCLKB-A/ PO5 MTIOC3B-A/ MTCLKC-A/ TMO0/PO2 MTIOC3A/ PO15 TMCI1-B RxD3-B ADTRG0#-B SSLA1-A L1 P25 CS5#-C/ EDACK1-B EDREQ0-B L2 P22 USB0_DRPD SCK0 L3 L4 L5 L6 L7 L8 VCC_USB P17 P12 TxD3-A SCL0/ RxD2-A IRQ7-B IRQ2-B P56 P52 P83 EDACK1-C RD# EDACK1-A ET_CRS/ RMII_CRS_D V ET_ETXD0/ RMII_TXD0 ET_RX_ER/ RMII_RX_ER ET_ERXD0/ RMII_RXD0 MTIOC3C-B SSLB3-A/ RxD2-B MTIOC4C-B TRCLK L9 L10 L11 L12 L13 M1 VCC P81 P77 P75 EDACK0-A CS7#-B CS5#-B MTIOC3D-B TRDATA1 PB6 P23 A14 EDACK0-B USB0_DPUPE -A USB0_ID MTIOC10B/ PO30 MTIOC3D-A/ MTCLKD-A/ PO3 MTIOC1A/ TMRI0-B/ PO0 TxD3-B M2 P20 SDA1/ TxD0 M3 PLLVCC R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 26 of 146 RX62N Group, RX621 Group Table 1.5 Pin No. 145-Pin TFLGA 1. Overview List of Pins and Pin Functions (145-Pin TFLGA) (5 / 5) Power Supply Clock System Control Timers (MTU, TMR, PPG, POE, WDT) Communication (SCI, CAN, RSPI, RIIC) I/O Port External Bus EXDMAC ETHERC EDMAC USB Others M4 P15 MTIOC0B/ TMCI2-A/ PO13 USB0_OVRC URA/ USB0_DPUPE -B TMRI2 SCK3-A IRQ5-B M5 P14 IRQ4-B M6 M7 M8 M9 M10 VSS_USB P55 P50 PC6 P80 WAIT#-B/ EDREQ0-C WR0#/ WR# A22/CS1#-C EDREQ0-A ET_ETXD3 ET_TX_EN/ RMII_TXD_E N ET_RX_DV ET_ERXD2 MTIC11V-A/ MTCLKA-B MTIOC3B-B ET_EXOUT MTIOC4D-B SSLB1-A/ TxD2-B MOSIA-A TRDATA0 TRDATA3 M11 M12 M13 N1 VSS PC2 PC1 A18-A A17-A MTCLKE-A MTCLKH-A SSLA3-A/ RxD5 SSLA2-A/ SCK5 P21 USB0_EXICE N USB0_VBUS/ USB0_OVRC URB/ USB0_VBUSE N-B MTIOC1B/ TMCI0-B/ PO1 MTIOC3C-A/ TMO2/ PO14 SCL1/RxD0 N2 P16 RxD3-A IRQ6-B N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 PLLVSS P13 USB0_DM USB0_DP P54 P51 VCC PC5 PC4 P76 P74 A21/CS2#-C/ WAIT#-C A20/CS3#-C CS6#-B CS4#-B ET_ETXD2 ET_TX_CLK ET_RX_CLK/ REF50CK ET_ERXD1/ RMII_RXD1 MTIC11W-A/ MTCLKD-B MTCLKC-B RSPCKA-A SSLA0-A EDACK0-C WR1#/BC1#/ WAIT#-D ET_LINKSTA MTIOC4B-B SSLB2-A/ SCK2 TRDATA2 TMO3 SDA0/ TxD2-A IRQ3-B/ ADTRG1# R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 27 of 146 RX62N Group, RX621 Group 1. Overview Table 1.6 Pin No. List of Pins and Pin Functions (144-Pin LQFP) (1 / 5) Power Supply Clock System Control Timers (MTU, TMR, PPG, POE, WDT) Communication (SCI, CAN, RSPI, RIIC) 144-Pin LQFP I/O Port External Bus EXDMAC ETHERC EDMAC USB Others 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AVSS P05 VCC P03 VSS P02 P01 P00 BSCANP EMLE WDTOVF# VSS MDE VCL MD1 MD0 XCIN XCOUT RES# XTAL VSS EXTAL VCC P35 P34 MTIOC0A/ TMCI3/ PO12 MTIOC0D/ PO11 MTIOC0C/ PO10/ RTCOUT MTIOC4DA/ TMCI2-B/ PO9 MTIOC4B-A/ TMRI3/ PO8 CS7#-C CS6#-C MTIOC2B/ PO7 MTIOC2A/ TMO1/ PO6 SCK6-B NMI IRQ4-A/ TRST# IRQ3-A IRQ2-A TMCI1-A TMCI0-A TMRI0-A SCK6-A RxD6-A TxD6-A IRQ10-A IRQ9-A IRQ8-A IRQ11-A/DA0 IRQ13-A/DA1 26 27 P33 P32 CRX0/ RxD6-B CTX0/ TxD6-B SSLB0-A 28 P31 IRQ1/ TMS 29 P30 RxD1/ MISOB-A RSPCKB-A/ SCK1 MOSIB-A/ TxD1 IRQ0/ TDI TCK TDO 30 31 P27 P26 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 28 of 146 RX62N Group, RX621 Group Table 1.6 Pin No. 1. Overview List of Pins and Pin Functions (144-Pin LQFP) (2 / 5) Power Supply Clock System Control Timers (MTU, TMR, PPG, POE, WDT) Communication (SCI, CAN, RSPI, RIIC) 144-Pin LQFP I/O Port External Bus EXDMAC ETHERC EDMAC USB Others 32 P25 CS5#-C/ EDACK1-B USB0_DPRPD MTIOC4CA/ MTCLKB-A/ PO5 MTIOC4A-A/ MTCLKA-A/ TMRI1/PO4 MTIOC3DA/ MTCLKD-A/ PO3 MTIOC3B-A/ MTCLKC-A/ TMO0/PO2 MTIOC1B/ TMCI0-B/ PO1 MTIOC1A/ TMRI0-B/ PO0 MTIOC3A/ PO15 RxD3-B ADTRG0#-B 33 P24 CS4#-C/ EDREQ1-B EDACK0-B USB0_VBUSEN -A USB0_DPUPEA SCK3-B 34 P23 TxD3-B 35 P22 EDREQ0-B USB0_DRPD SCK0 36 P21 USB0_EXICEN SCL1/RxD0 37 P20 USB0_ID SDA1/ TxD0 TxD3-A IRQ7-B 38 39 40 PLLVCC P17 P16 USB0_VBUS/ USB0_OVRCU RB/ USB0_VBUSEN -B MTIOC3CA/ TMO2/ PO14 RxD3-A IRQ6-B 41 42 PLLVSS P15 MTIOC0B/ TMCI2-A/ PO13 USB0_OVRCU RA/ USB0_DPUPEB TMRI2 SCK3-A IRQ5-B 43 P14 IRQ4-B 44 45 46 47 48 49 50 51 52 53 54 BCLK VSS_USB VCC_USB P13 P12 TMO3 TMCI1-B SDA0/ TxD2-A SCL0/ RxD2-A IRQ3-B/ ADTRG1# IRQ2-B USB0_DM USB0_DP P56 P55 P54 P53 P52 EDACK1-C WAIT#-B/ EDREQ0-C EDACK0-C ET_EXOUT ET_LINKSTA MTIOC3C-B MTIOC4D-B MTIOC4B-B TRDATA3 TRDATA2 RD# SSLB3-A/ RxD2-B R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 29 of 146 RX62N Group, RX621 Group Table 1.6 Pin No. 1. Overview List of Pins and Pin Functions (144-Pin LQFP) (3 / 5) Power Supply Clock System Control Timers (MTU, TMR, PPG, POE, WDT) Communication (SCI, CAN, RSPI, RIIC) 144-Pin LQFP I/O Port External Bus EXDMAC ETHERC EDMAC USB Others 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VSS VCC VCC VSS P51 P50 WR1#/BC1#/ WAIT#-D WR0#/ WR# SSLB2-A/ SCK2 SSLB1-A/ TxD2-B P83 EDACK1-A ET_CRS/ RMII_CRS_DV MTIOC4C-B TRCLK PC7 PC6 PC5 P82 P81 P80 PC4 PC3 P77 P76 PC2 P75 P74 PC1 A23/ CS0#-B A22/ CS1#-C A21/CS2#-C/ WAIT#-C EDREQ1-A EDACK0-A EDREQ0-A A20/CS3#-C A19-A CS7#-B CS6#-B A18-A CS5#-B CS4#-B A17-A ET_COL ET_ETXD3 ET_ETXD2 ET_ETXD1/ RMII_TXD1 ET_ETXD0/ RMII_TXD0 ET_TX_EN/ RMII_TXD_EN ET_TX_CLK ET_TX_ER ET_RX_ER/ RMII_RX_ER ET_RX_CLK/ REF50CK ET_RX_DV ET_ERXD0/ RMII_RXD0 ET_ERXD1/ RMII_RXD1 ET_ERXD2 MTIC11U-A/ MTCLKB-B MTIC11V-A/ MTCLKA-B MTIC11W-A/ MTCLKD-B MTIOC4A-B MTIOC3D-B MTIOC3B-B MTCLKC-B MTCLKF-A MISOA-A MOSIA-A RSPCKA-A TRSYNC TRDATA1 TRDATA0 SSLA0-A TxD5 MTCLKE-A SSLA3-A/ RxD5 MTCLKH-A SSLA2-A/ SCK5 PC0 A16-A ET_ERXD3 MTCLKG-A SSLA1-A P73 PB7 PB6 PB5 CS3#-B A15 A14 A13 ET_WOL MTIOC10D/ PO31 MTIOC10B/ PO30 MTIOC10C/ MTCLKF-B/ PO29 MTIOC10A/ MTCLKE-B/ PO28 81 PB4 A12 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 30 of 146 RX62N Group, RX621 Group Table 1.6 Pin No. 1. Overview List of Pins and Pin Functions (144-Pin LQFP) (4 / 5) Power Supply Clock System Control Timers (MTU, TMR, PPG, POE, WDT) Communication (SCI, CAN, RSPI, RIIC) 144-Pin LQFP I/O Port External Bus EXDMAC ETHERC EDMAC USB Others 82 PB3 A11 MTIOC9D/ MTCLKH-B/ PO27 MTIOC9B/ MTCLKG-B/ PO26 MTIOC9C/ PO25 ET_MDC ET_MDIO MTIOC9A/ PO24 MTIOC8B/ PO23 MTIOC8A/ PO22 MTIOC7B/ PO21 MISOA-B MOSIA-B RSPCKA-B 83 PB2 A10 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 VCC SDCLK VSS VSS VCC PB1 P72 P71 PB0 PA7 PA6 PA5 A9 CS2#-B CS1#-B A8 A7 A6 A5 PA4 A4 MTIOC7A/ PO20 SSLA0-B PA3 PA2 PA1 PA0 P67 P66 P65 PE7 PE6 A3 A2 A1 A0/BC0#/ CS7#-A/ DQM1 CS6#-A/ DQM0 CS5#-A/ CKE D15 D14 MTIOC6D/ PO19 MTIOC6C/ PO18 MTIOC6B/ PO17 MTIOC6A/ PO16 SSLA3-B SSLA2-B SSLA1-B MISOB-B MOSIB-B IRQ7-A IRQ6-A P70 PE5 PE4 PE3 PE2 PE1 PE0 D13 D12 D11 D10 D9 D8 POE8# POE9# RSPCKB-B SSLB0-B IRQ5-A SSLB3-B SSLB2-B SSLB1-B R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 31 of 146 RX62N Group, RX621 Group Table 1.6 Pin No. 1. Overview List of Pins and Pin Functions (144-Pin LQFP) (5 / 5) Power Supply Clock System Control Timers (MTU, TMR, PPG, POE, WDT) Communication (SCI, CAN, RSPI, RIIC) 144-Pin LQFP I/O Port External Bus EXDMAC ETHERC EDMAC USB Others 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 VREFH AVCC VREFL VCC VSS VCC VSS P64 P63 P62 P61 CS4#-A/ WE# CS3#-A/ CAS# CS2#-A/ RAS# CS1#-A/ SDCS# P60 CS0#-A PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 P93 P92 P91 D7 D6 D5 D4 D3 D2 D1 D0 A19-B A18-B A17-B MTIC5U/ POE0# MTIC5V/ POE1# MTIC5W/ POE2# MTIC11U-B/ POE3# MTIC11V-B/ POE4# MTIC11W-B/ POE5# POE6# POE7# P90 A16-B P47 P46 P45 P44 P43 P42 P41 IRQ15-B/AN7 IRQ14/AN6 IRQ13-B/AN5 IRQ12/AN4 IRQ11-B/AN3 IRQ10-B/AN2 IRQ9-B/AN1 P40 IRQ8-B/AN0 P07 IRQ15-A/ ADTRG0#-A R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 32 of 146 RX62N Group, RX621 Group 1. Overview Table 1.7 Pin No. 100-PIn LQFP List of Pins and Pin Functions (100-Pin LQFP) (1 / 4) Power Supply Clock System Control Timers (MTU, TMR, PPG, POE) Communication (SCI, CAN, RSPI, RIIC) I/O Port External Bus ETHERC EDMAC USB Others 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCC EMLE VSS MDE VCL MD1 MD0 XCIN XCOUT RES# XTAL VSS EXTAL VCC P35 P34 MTIOC0A/ TMCI3/ PO12 MTIOC0D/ PO11 MTIOC0C/ PO10/ RTCOUT MTIOC4DA/ TMCI2/ PO9 MTIOC4BA/ TMRI3/ PO8 CS7# MTIOC2B/ PO7 MTIOC2A/ TMO1/ PO6 USB0_DPRPD MTIOC4C/ MTCLKB-A/ PO5 MTIOC4A/ MTCLKA/ TMRI1/PO4 MTIOC3D/ MTCLKD-A/ PO3 MTIOC3B/ MTCLKC-A/ TMO0/PO2 SCK6 NMI IRQ4-A/ TRST# IRQ3-A IRQ2-A 17 18 P33 P32 CRX0/ RxD6 CTX0/ TxD6 SSLB0-A 19 P31 IRQ1/ TMS 20 P30 RxD1/ MISOB-A IRQ0/ TDI 21 P27 RSPCKBA/ SCK1 MOSIB-A/ TxD1 RxD3 TCK 22 P26 CS6# TDO 23 P25 CS5# ADTRG0#-B 24 P24 CS4#/ USB0_VBUSE N-A USB0_DPUPEA USB0_DRPD SCK3 25 P23 TxD3 26 P22 SCK0 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 33 of 146 RX62N Group, RX621 Group Table 1.7 Pin No. 100-PIn LQFP 1. Overview List of Pins and Pin Functions (100-Pin LQFP) (2 / 4) Power Supply Clock System Control Timers (MTU, TMR, PPG, POE) Communication (SCI, CAN, RSPI, RIIC) I/O Port External Bus ETHERC EDMAC USB Others 27 P21 USB0_EXICEN MTIOC1B/ TMCI0/ PO1 MTIOC1A/ TMRI0/ PO0 RxD0 28 P20 USB0_ID TxD0 29 30 PLLVCC P16 USB0_VBUS/ USB0_OVRCU RB/ USB0_VBUSE N-B MTIOC3C/ TMO2/ PO14 IRQ6-B 31 32 PLLVSS P14 USB0_OVRCU RA/ USB0_DPUPEB MTIOC3A/ TMRI2/ PO15 MTIOC0B/ TMO3/ PO13 TMCI1 SDA0/ TxD2-A SCL0/ RxD2-A IRQ4-B 33 P13 IRQ3-B/ ADTRG1# IRQ2-B 34 35 36 37 38 39 40 41 42 43 44 45 46 47 BCLK VSS_USB VCC_USB P12 USB0_DM USB0_DP P55 P54 P53 P52 P51 P50 PC7 PC6 PC5 WAIT#-B MTIOC4D-B MTIOC4B-B RD# WR1#/BC1#/ WAIT#-D WR0#/ WR# A23/ CS0# A22/ CS1# A21/CS2#/ WAIT#-C A20/CS3# A19 A18 A17 A16 ET_COL ET_ETXD3 ET_ETXD2 MTIC11U-A/ MTCLKB-B MTIC11V-A/ MTCLKA-B MTIC11WA/ MTCLKD-B MTCLKC-B MTCLKF-A MTCLKE-A MTCLKH-A MTCLKG-A SSLB3-A/ RxD2-B SSLB2-A/ SCK2 SSLB1-A/ TxD2-B MISOA-A MOSIA-A RSPCKA-A 48 49 50 51 52 PC4 PC3 PC2 PC1 PC0 ET_TX_CLK ET_TX_ER ET_RX_DV ET_ERXD2 ET_ERXD3 SSLA0-A TxD5 SSLA3-A/ RxD5 SSLA2-A/ SCK5 SSLA1-A R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 34 of 146 RX62N Group, RX621 Group Table 1.7 Pin No. 100-PIn LQFP 1. Overview List of Pins and Pin Functions (100-Pin LQFP) (3 / 4) Power Supply Clock System Control Timers (MTU, TMR, PPG, POE) Communication (SCI, CAN, RSPI, RIIC) I/O Port External Bus ETHERC EDMAC USB Others 53 PB7 A15 ET_CRS/ RMII_CRS_D V ET_ETXD1/ RMII_TXD1 ET_ETXD0/ RMII_TXD0 ET_TX_EN/ RMII_TXD_E N ET_RX_ER/ RMII_RX_ER ET_RX_CLK/ REF50CK ET_ERXD0/ RMII_RXD0 MTIOC10D/ PO31 MTIOC10B/ PO30 MTIOC10C/ MTCLKF-B/ PO29 MTIOC10A/ MTCLKE-B/ PO28 MTIOC9D/ MTCLKH-B/ PO27 MTIOC9B/ MTCLKG-B/ PO26 MTIOC9C/ PO25 54 55 PB6 PB5 A14 A13 56 PB4 A12 57 PB3 A11 58 PB2 A10 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 VSS VCC PB1 A9 PB0 A8 ET_ERXD1/ RMII_RXD1 MTIOC9A/ PO24 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PD7 A7 A6 A5 A4 A3 A2 A1 A0/BC0# D15 D14 D13 D12 D11 D10 D9 D8 D7 ET_WOL ET_EXOUT ET_LINKSTA ET_MDC ET_MDIO MTIOC8B/ PO23 MTIOC8A/ PO22 MTIOC7B/ PO21 MTIOC7A/ PO20 MTIOC6D/ PO19 MTIOC6C/ PO18 MTIOC6B/ PO17 MTIOC6A/ PO16 MISOA-B MOSIA-B RSPCKA-B SSLA0-B SSLA3-B SSLA2-B SSLA1-B MISOB-B MOSIB-B RSPCKB-B SSLB0-B IRQ7 IRQ6-A IRQ5 POE8# POE9# SSLB3-B SSLB2-B SSLB1-B MTIC5U/ POE0# R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 35 of 146 RX62N Group, RX621 Group Table 1.7 Pin No. 100-PIn LQFP 1. Overview List of Pins and Pin Functions (100-Pin LQFP) (4 / 4) Power Supply Clock System Control Timers (MTU, TMR, PPG, POE) Communication (SCI, CAN, RSPI, RIIC) I/O Port External Bus ETHERC EDMAC USB Others 80 81 82 83 84 PD6 PD5 PD4 PD3 PD2 D6 D5 D4 D3 D2 MTIC5V/ POE1# MTIC5W/ POE2# MTIC11U-B/ POE3# MTIC11V-B/ POE4# MTIC11WB/ POE5# POE6# POE7# IRQ15-B/AN7 IRQ14/AN6 IRQ13-B/AN5 IRQ12/AN4 IRQ11/AN3 IRQ10/AN2 IRQ9/AN1 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 AVSS VREFH AVCC VREFL PD1 PD0 P47 P46 P45 P44 P43 P42 P41 D1 D0 P40 IRQ8/AN0 P07 IRQ15-A/ ADTRG0#-A P05 DA1/IRQ13-A R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 36 of 146 RX62N Group, RX621 Group 1. Overview Table 1.8 Pin No. List of Pins and Pin Functions (85-Pin TFLGA) (1 / 3) Power Supply Clock System Control 85-Pin TFLGA External I/O Port Bus USB Timers (MTU, TMR, PPG) Communication (SCI, CAN, RSPI, RIIC) Others A1 P05 DA1/ IRQ13A A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 D4 AVCC VREFL P43 P47 PD1 PD4 PD5 PD7 PD6 VCC AVSS VREFH P42 P46 PD0 PD2 PD3 PA3 PA1 P03 VSS P40 P41 P44 P45 MD1 BSCANP PA5 PA0 MDE EMLE MD0 RES# A5 A0 MTIOC7B/PO21 MTIOC6A/PO16 RSPCKA SSLA1 IRQ8/ AN0 IRQ9/ AN1 IRQ12/ AN4 IRQ13B/AN5 D0 D2 D3 A3 A1 MTIC11W MTIC11V MTIOC6D/PO19 MTIOC6B/PO17 SSLA2 IRQ11A/DA0 IRQ10/ AN2 IRQ14/ AN6 D1 D4 D5 D7 D6 MTIC11U MTIC5W MTIC5U MTIC5V IRQ11B/AN3 IRQ15/ AN7 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 37 of 146 RX62N Group, RX621 Group Table 1.8 Pin No. 1. Overview List of Pins and Pin Functions (85-Pin TFLGA) (2 / 3) Power Supply Clock System Control 85-Pin TFLGA External I/O Port Bus USB Timers (MTU, TMR, PPG) Communication (SCI, CAN, RSPI, RIIC) Others D8 D9 D10 E1 E2 E3 E8 E9 E10 F1 F2 F3 F8 F9 F10 G1 G2 G3 G8 G9 G10 H1 H2 H3 H4 H5 VCL PA6 PA2 XCIN XCOUT P34 VSS PB0 PA4 XTAL EXTAL P32 VCC PB2 PA7 P35 P33 P27 PB3 PB5 PB1 P31 P30 P26 PLLVCC P14 USB0_OVRCUR A/USB0_DPUPEB MTIOC3A/TMRI2/PO15 IRQ4-B CS6# CS7# A11 A13 A9 MTIOC0D/PO11 MTIOC2B/PO7 MTIOC9D/MTCLKH-B/PO27 MTIOC10C/MTCLKF-B/PO29 MTIOC9C/PO25 MTIOC4D/TMCI2/PO9 MTIOC4B/TMRI3/PO8 MTIOC2A/TMO1/PO6 SSLB0 RxD1/MISOB TxD1/MOSIB IRQ1/ TMS IRQ0/ TDI TDO RxD6/CRX0 SCK1/RSPCKB A10 A7 MTIOC9B/MTCLKG-B/ PO26 MTIOC8B/PO23 MISOA NMI IRQ3-A TCK MTIOC0C/PO10/RTCOUT TxD6/CTX0 IRQ2-A A8 A4 MTIOC9A/PO24 MTIOC7A/PO20 SSLA0 MTIOC0A/TMCI3/PO12 SCK6 IRQ4-A/ TRST# A6 A2 MTIOC8A/PO22 MTIOC6C/PO18 MOSIA SSLA3 H6 P13 MTIOC0B/TMO3/PO13 TxD2-A/SDA0 IRQ3-B/ ADTRG 1# H7 H8 H9 H10 J1 J2 J3 BCLK P53 PB6 PB7 PB4 P25 P23 P24 CS4# A14 A15 A12 CS5# USB0_DPRPD USB0_DPUPE-A USB0_VBUSENA MTIOC10B/PO30 MTIOC10D/PO31 MTIOC10A/MTCLKE-B/PO28 MTIOC4C/MTCLKB/PO5 MTIOC3D/MTCLKD/PO3 MTIOC4A/MTCLKA-A/TMRI1/ PO4 RxD3 TxD3 SCK3 ADTRG 0# R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 38 of 146 RX62N Group, RX621 Group Table 1.8 Pin No. 1. Overview List of Pins and Pin Functions (85-Pin TFLGA) (3 / 3) Power Supply Clock System Control 85-Pin TFLGA External I/O Port Bus USB Timers (MTU, TMR, PPG) Communication (SCI, CAN, RSPI, RIIC) Others J4 P16 USB0_VBUS/ USB0_OVRCUR B/ USB0_VBUSENB MTIOC3C/TMO2/PO14 IRQ6 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 VCC_USB USB0_DM P52 P51 PC3 PC0 P21 P22 P20 PLLVSS P12 USB0_DP VSS_USB P50 PC2 PC1 WR0# A18 A17 MTCLKE-A MTCLKH-A TxD2-B/SSLB1 RxD5 SCK5 TMCI1 RxD2-A/SCL0 IRQ2-B RD# WAIT# A19 A16 USB0_EXICEN USB0_DRPD USB0_ID MTCLKF-A MTCLKG-A MTIOC1B/TMCI0/PO1 MTIOC3B/MTCLKC/TMO0/PO2 MTIOC1A/TMRI0/PO0 RxD0/SCL1 SCK0 TxD0/SDA1 RxD2-B/SSLB3 SCK2/SSLB2 TxD5 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 39 of 146 RX62N Group, RX621 Group 1. Overview 1.5 Pin Functions Table 1.8 lists the pin functions. Table 1.9 Classifications Pin Functions (1 / 7) Pin Name I/O Description Power supply VCC VCL VSS PLLVCC PLLVSS Input Input Input Input Input Output Input Output Output Output Input Input Input Input Power supply pin. Connect it to the system power supply. Connect this pin to VSS via a 0.1-F capacitor. The capacitor should be placed close to the pin. Ground pin. Connect it to the system power supply (0 V). Power supply pin for the PLL circuit. Connect it to the system power supply. Ground pin for the PLL circuit. Pins for a crystal resonator. An external clock signal can be input through the EXTAL pin. Outputs the external bus clock for external devices. Outputs the clock dedicated for the SDRAM. Input/output pins for the subclock generation circuit. Connect a crystal resonator between XCOUT and XCIN. Pins for setting the operating mode. The signal levels on these pins must not be changed during operation. Reset signal input pin. This LSI enters the reset state when this signal goes low. Input pin to enable the connection of the on-chip emulator signal. When the on-chip emulator is used, this pin should be driven high. When not used, it should be driven low. Boundary scan pin. Boundary scan is enabled when this pin goes high. When not used, it should be driven low. Connect this pin to VSS via pull-down resister. On-chip emulator pins or boundary scan pins. When the EMLE pin is driven high, these pins are dedicated for the on-chip emulator. Clock XTAL EXTAL BCLK SDCLK XCOUT XCIN Operating mode control System control MD0, MD1, MDE RES# EMLE BSCANP CNVSS On-chip emulator CNVSS TRST# TMS TDI TCK TDO TRCLK TRSYNC TRDATA0-A/TRDATA3-B Address bus A0 to A15 A16-A/A16-B to A23-A/A23-B D0 to D31 Input Input Input Input Input Input Output Output Output Output Output This pin outputs the clock for synchronization with the trace data. This pin indicates that output from the TRDATA0 to TRDATA3 pins is valid. These pins output the trace information. Output pins for the address. Data bus I/O Input and output pins for the bidirectional data bus. R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 40 of 146 RX62N Group, RX621 Group Table 1.9 Classifications 1. Overview Pin Functions (2 / 7) Pin Name I/O Description Bus control RD# WR# WR0# to WR3# Output Output Output Strobe signal which indicates that reading from the external bus interface space is in progress. Strobe signal which indicates that writing to the external bus interface space is in progress, in 1-write strobe mode. Strobe signals which indicate that any group of data bus pins (D7 to D0, D15 to D8, D23 to D16, and D31 to D24) is valid in writing to the external bus interface space, in byte strobe mode. Strobe signals which indicate that any group of data bus pins (D7 to D0, D15 to D8, D23 to D16, and D31 to D24) is valid in access to the external bus interface space, in 1-write strobe mode. Output pin for SDRAM write enable signals. Output pin for SDRAM column address strobe signals. Output pin for SDRAM row address strobe signals. Output pin for SDRAM clock enable signals. Output pins for SDRAM I/O data mask enable signals. Output pin for SDRAM chip select signals. Select signals for areas 0 to 7. BC0# to BC3# Output WE# CAS# RAS# CKE DQM0 to DQM34 SDCS# CS0#-A/CS0#-B CS1#-A/CS1#-B/CS1#-C CS2#-A/CS2#-B/CS2#-C CS3#-A/CS3#-B/CS3#-C CS4#-A/CS4#-B/CS4#-C CS5#-A/CS5#-B/CS5#-C CS6#-A/CS6#-B/CS6#-C CS7#-A/CS7#-B/CS7#-C WAIT#-A/WAIT#-B/ WAIT#-C/WAIT#-D EXDMA controller EDREQ0-A/EDREQ0-B/ EDREQ0-C EDREQ1-A/EDREQ1-B/ EDREQ1-C EDACK0-A/EDACK0-B/ EDACK0-C EDACK1-A/EDACK1-B/ EDACK1-C Interrupt NMI IRQ0-A/IRQ0-B IRQ1-A/IRQ1-B IRQ2-A/IRQ2-B IRQ3-A/IRQ3-B IRQ4-A/IRQ4-B IRQ5-A/IRQ5-B IRQ6-A/IRQ6-B IRQ7-A/IRQ7-B IRQ8-A/IRQ8-B IRQ9-A/IRQ9-B IRQ10-A/IRQ10-B IRQ11-A/IRQ11-B IRQ12 IRQ13-A/IRQ13-B IRQ14 IRQ15-A/IRQ15-B Output Output Output Output Output Output Output Input Input Input Output Output Input Input Input pins for wait request signals in access to the external space. Input pins for external requests of channel 0. Input pins for external requests of channel 1. Output pins for single address transfer acknowledge signals of channel 0. Output pins for single address transfer acknowledge signals of channel 1. Non-maskable interrupt request signal. Interrupt request signals. R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 41 of 146 RX62N Group, RX621 Group Table 1.9 Classifications 1. Overview Pin Functions (3 / 7) Pin Name I/O Description Multi-function timer pulse unit MTIOC0A MTIOC0B MTIOC0C MTIOC0D MTIOC1A MTIOC1B MTIOC2A MTIOC2B MTIOC3A MTIOC3B-A/MTIOC3B-B MTIOC3C-A/MTIOC3C-B MTIOC3D-A/MTIOC3D-B MTIOC4A-A/MTIOC4A-B MTIOC4B-A/MTIOC4B-B MTIOC4C-A/MTIOC4C-B MTIOC4D-A/MTIOC4D-B MTIC5U-A/MTIC5U-B MTIC5V-A/MTIC5V-B MTIC5W-A/MTIC5W-B MTIOC6A MTIOC6B MTIOC6C MTIOC6D MTIOC7A MTIOC7B MTIOC8A MTIOC8B MTIOC9A MTIOC9B MTIOC9C MTIOC9D MTIOC10A MTIOC10B MTIOC10C MTIOC10D MTIC11U-A/MTIC11U-B MTIC11V-A/MTIC11V-B MTIC11W-A/MTIC11W-B MTCLKA-A/MTCLKA-B MTCLKB-A/MTCLKB-B MTCLKC-A/MTCLKC-B MTCLKD-A/MTCLKD-B MTCLKE-A/MTCLKE-B MTCLKF-A/MTCLKF-B MTCLKG-A/MTCLKG-B MTCLKH-A/MTCLKH-B I/O The TGRA0 to TGRD0 input capture input/output compare output/PWM output pins. I/O I/O I/O The TGRA1 and TGRB1 input capture input/output compare output/PWM output pins. The TGRA2 and TGRB2 input capture input/output compare output/PWM output pins. The TGRA3 to TGRD3 input capture input/output compare output/PWM output pins. I/O The TGRA4 and TGRB4 input capture input/output compare output/PWM output pins. Input The TGRU5, TGRV5, and TGRW5 input capture input/dead time compensation input pins. The TGRA6 to TGRD6 input capture input/output compare output/PWM output pins. I/O I/O I/O I/O The TGRA7 and TGRB7 input capture input/output compare output/PWM output pins. The TGRA8 and TGRB8 input capture input/output compare output/PWM output pins. The TGRA9 to TGRD9 input capture input/output compare output/PWM output pins. I/O The TGRA10 to TGRB10 input capture input/output compare output/PWM output pins. Input The TGRU11, TGRV11, and TGRW11 input capture input/dead time compensation input pins. Input pins for external clock signals. Input Port output enable Programmable pulse generator POE0# to POE9# PO0 to PO31 Input Output Input pins for request signals to place the MTU large-current pin in the high impedance state. Output pins for the pulse signals. R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 42 of 146 RX62N Group, RX621 Group Table 1.9 Classifications 1. Overview Pin Functions (4 / 7) Pin Name I/O Description 8-bit timer TMO0 to TMO3 TMCI0-A/TMCI0-B TMCI1-A/TMCI1-B TMCI2-A/TMCI2-B TMCI3-A/TMCI3-B TMRI0-A/TMRI0-B TMRI1 TMRI2 TMRI3-A/TMRI3-B Output Input Output pins for the compare match signals. Input pins for the external clock signals that drive for the counters. Input Input pins for the counter-reset signals. Watchdog timer Serial communications interface WDTOVF# TxD0 TxD1-A/TxD1-B TxD2-A/TxD2-B TxD3-A/TxD3-B TxD5 TxD6-A/TxD6-B RxD0 RxD1-A/RxD1-B RxD2-A/RxD2-B RxD3-A/RxD3-B RxD5 RxD6-A/RxD6-B SCK0 SCK1-A/SCK1-B SCK2-A/SCK2-B SCK3-A/SCK3-B SCK5 SCK6-A/SCK6-B Output Output Output pin for the counter-overflow signal in watchdog-timer mode. Output pins for data transmission. Input Input pins for data reception. I/O Input/output pins for clock signals. I2C bus interface SCL0, SCL1 SDA0, SDA1 I/O I/O Input/output pins for I2C bus interface clocks. Bus can be directly driven by the NMOS open drain output. Input/output pins for I2C bus interface data. Bus can be directly driven by the NMOS open drain output. R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 43 of 146 RX62N Group, RX621 Group Table 1.9 Classifications 1. Overview Pin Functions (5 / 7) Pin Name I/O Description Ethernet controller REF50CK RMII_CRS_DV RMII_TXD0, RMII_TXD1 RMII_RXD0, RMII_RXD1 RMII_TXD_EN RMII_RX_ER ET_CRS ET_RX_DV ET_EXOUT ET_LINKSTA ET_ETXD0 to ET_ETXD3 ET_ERXD0 to ET_ERXD3 ET_TX_EN ET_TX_ER ET_RX_ER ET_TX_CLK Input Input Output Input Output Input Input Input Output Input Output Input Output Output Input Input 50-MHz reference clock. This pin inputs reference signals for transmission/reception timings in RMII mode. Indicates that there are carrier detection signals and valid receive data on RMII_RXD1 and RMII_RXD0 in RMII mode. 2-bit transmit data in RMII mode. 2-bit receive data in RMII mode. Output pin for data transmit enable signals in RMII mode. Indicates an error has occurred during reception of data in RMII mode. Carrier detection/data reception enable pin. Indicates that there are valid receive data on ET_ERXD3 to ET_ERXD0. General-purpose external output pin. Inputs link status from the PHY-LSI. 4 bits of MII transmit data. 4 bits of MII receive data. Transmit enable pin. Indicates that transmit data is ready on ET_ETXD3 to ET_ETXD0. Transmit error pin. Notifies the PHY_LSI of an error during transmission. Receive error pin. Recognizes an error during reception. Transmit clock pin. This pin inputs reference signals for output timings from ET_TX_EN, ET_ETXD3 to ET_ETXD0, and ET_TX_ER. Receive clock pin. This pin inputs reference signals for input timings to ET_RX_DV, ET_ERXD3 to ET_ERXD0, and ET_RX_ER. Inputs collision detection signals. Receives Magic packets. Outputs reference clock signals for information transfer via ET_MDIO. Inputs or outputs bidirectional signals for exchange of management information between the RX62N/RX621 Group and the PHY-LSI. ET_RX_CLK Input ET_COL ET_WOL ET_MDC ET_MDIO Input Output Output I/O R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 44 of 146 RX62N Group, RX621 Group Table 1.9 Classifications 1. Overview Pin Functions (6 / 7) Pin Name I/O Description USB 2.0 host/function module VCC_USB VSS_USB USB0_DP USB1_DP USB0_DM USB1_DM USB0_DPRPD USB1_DPRPD USB0_DRPD USB1_DRPD USB0_EXICEN USB1_EXICEN USB0_ID USB1_ID USB0_VBUSEN-A/ USB0_VBUSEN-B USB1_VBUSEN-A/ USB1_VBUSEN-B USB0_DPUPE-A/ USB0_DPUPE-B USB1_DPUPE-A/ USB1_DPUPE-B USB0_OVRCURA/ USB0_OVRCURB USB1_OVRCURA/ USB1_OVRCURB USB0_VBUS USB1_VBUS Input Input I/O I/O Output Output Output Input Output Power-supply pin for the USB. Connect this pin to the system power supply even when the USB is not to be used. Ground pin for the USB. Connect this pin to the system power supply (0 V) even when the USB is not to be used. Inputs or outputs D+ data for the USB bus. Inputs or outputs D- data for the USB bus. Enable D+ pull-down. Enable D- pull-down. Connect these pins to the OTG power supply IC. Connect these pins to the OTG power supply IC. VBUS power enable pins for the USB. Output Pull-up pins for the USB. Input Over current pins for the USB. Input Input Output I/O I/O I/O I/O I/O Output Input pins for detection of connection and disconnection of the USB cable. Input pins for the CAN. Output pins for the CAN. Clock input/output pins for the RSPI. Clock input/output pins for the RSPI Input or output data output from the master for the RSPI. Input or output data output from the slave for the RSPI. Select the slave for the RSPI. CAN module CRX0 CTX0 Serial peripheral interfaces RSPCKA-A/ RSPCKA-B RSPCKB-A/ RSPCKB-B MOSIA-A/MOSIA-B MOSIB-A/MOSIB-B MISOA-A/MISOA-B MISOB-A/MISOB-B SSLA0-A/SSLA0-B SSLA1-A/SSLA1-B SSLA2-A/SSLA2-B SSLA3-A/SSLA3-B SSLB0-A/SSLB0-B SSLB1-A/SSLB1-B SSLB2-A/SSLB2-B SSLB3-A/SSLB3-B I/O Output Realtime clock A/D converter RTCOUT AN0 to AN7 ADTRG0#-A/ADTRG0#-B ADTRG1# Output Input Input Output Output pin for 1-Hz clock. Input pins for the analog signals to be processed by the A/D converter. Input pins for the external trigger signals that start the A/D conversion. Output pins for the analog signals from the D/A converter. D/A converter DA0, DA1 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 45 of 146 RX62N Group, RX621 Group Table 1.9 Classifications 1. Overview Pin Functions (7 / 7) Pin Name I/O Description Analog power supply AVCC Input Analog power supply pin for the A/D and D/A converters. When the A/D and D/A converters are not in use, connect this pin to the system power supply. Ground pin for the A/D and D/A converters. Connect this pin to the system power supply (0 V). Reference power supply pin for the A/D and D/A converters. When the A/D and D/A converters are not in use, connect this pin to the system power supply. Reference ground pin for the A/D and D/A converters. Make sure to connect this pin to the analog reference power supply (0 V). When the A/D and D/A converters are not in use, connect this pin to the system power supply (0 V). For details, see section 34.6.7, Ranges of Settings for Analog Power Supply and Other Pins. 6-bit input/output pins. 8-bit input/output pins. 8-bit input/output pins. 5-bit input/output pins. 1-bit input pin. 8-bit input/output pins. 7-bit input/output pins. 1-bit input pin. 8-bit input/output pins. 8-bit input/output pins. 6-bit input/output pins. 8-bit input/output pins. 8-bit input/output pins. 8-bit input/output pins. 8-bit input/output pins. 8-bit input/output pins. 8-bit input/output pins. 5-bit input/output pins. 8-bit input/output pins. AVSS VREFH Input Input VREFL Input I/O ports P00 to P03, P05, P07 P10 to P17 P20 to P27 P30 to P34 P35 P40 to P47 P50 to P52, P54 to P57 P53 P60 to P67 P70 to P77 P80 to P85 P90 to P97 PA0 to PA7 PB0 to PB7 PC0 to PC7 PD0 to PD7 PE0 to PE7 PF0 to PF4 PG0 to PG7 I/O I/O I/O I/O Input I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 46 of 146 RX62N Group, RX621 Group 2. CPU 2. CPU The RX CPU has sixteen general-purpose registers, nine control registers, and one accumulator used for DSP instructions. General-purpose register b31 b0 R0 (SP) * R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Control register b31 b0 ISP USP INTB PC PSW BPC BPSW FINTV FPSW DSP instruction register b63 (Interrupt stack pointer) (User stack pointer) (Interrupt table register) (Program counter) (Processor status word) (Backup PC) (Backup PSW) (Fast interrupt vector register) (Floating-point status word) b16 b15 b0 ACC (Accumulator) Note: * The stack pointer (SP) can be the interrupt stack pointer (ISP) or user stack pointer (USP), according to the value of the U bit in the PSW. Figure 2.1 Register Set of the CPU R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 47 of 146 RX62N Group, RX621 Group 2. CPU 2.1 General-Purpose Registers (R0 to R15) This CPU has sixteen general-purpose registers (R0 to R15). R1 to R15 can be used as data registers or address registers. R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor status word (PSW). 2.2 (1) Control Registers Interrupt Stack Pointer (ISP)/User Stack Pointer (USP) The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP). Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the processor status word (PSW). Set the ISP or USP to a multiple of four, as this reduces the numbers of cycles required to execute interrupt sequences and instructions entailing stack manipulation. (2) Interrupt Table Register (INTB) The interrupt table register (INTB) specifies the address where the relocatable vector table starts. Set INTB to a multiple of four. (3) Program Counter (PC) The program counter (PC) indicates the address of the instruction being executed. (4) Processor Status Word (PSW) The processor status word (PSW) indicates results of instruction execution or the state of the CPU. (5) Backup PC (BPC) The backup PC (BPC) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the program counter (PC) are saved in the BPC. (6) Backup PSW (BPSW) The backup PSW (BPSW) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The allocation of bits in the BPSW corresponds to that in the PSW. (7) Fast Interrupt Vector Register (FINTV) The fast interrupt vector register (FINTV) is provided to speed up response to interrupts. The FINTV register specifies a branch destination address when a fast interrupt has been generated. (8) Floating-Point Status Word (FPSW) The floating-point status word (FPSW) indicates the results of floating-point operations. When an exception handling enable bit (Ej) enables the exception handling (Ej = 1), the exception cause can be identified by checking the corresponding Cj flag in the exception handling routine. If the exception handling is masked (Ej = 0), the occurrence of exception can be checked by reading the Fj flag at the end of a series of processing. Once the Fj flag has been set to 1, this value is retained until it is cleared to 0 by software (j = X, U, Z, O, or V). R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 48 of 146 RX62N Group, RX621 Group 2. CPU (9) Accumulator (ACC) The accumulator (ACC) is a 64-bit register used for DSP instructions. The accumulator is also used for the multiply and multiply-and-accumulate instructions; EMUL, EMULU, FMUL, MUL, and RMPA, in which case the prior value in the accumulator is modified by execution of the instruction. Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively. Use the MVFACHI and MVFACMI instructions for reading data from the accumulator. The MVFACHI and MVFACMI instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively. R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 49 of 146 RX62N Group, RX621 Group 3. Address Space 3. 3.1 Address Space Address Space This LSI has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is, linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas. Figure 3.1 shows the memory maps in the respective operating modes. Accessible areas will differ according to the operating mode and states of control bits. Single-chip mode*2 0000 0000h 0001 8000h 0008 0000h Peripheral I/O registers 0010 0000h 0010 8000h 007F 8000h 007F A000h Reserved area*1 007F C000h 007F C500h Peripheral I/O registers Reserved area 007F FC00h 0080 0000h Reserved area 00F8 0000h 0100 0000h *1 *1 On-chip ROM enabled extended mode 0000 0000h 0001 8000h 0008 0000h Peripheral I/O registers 0010 0000h 0010 8000h 007F 8000h 007F A000h Reserved area*1 007F C000h 007F C500h Peripheral I/O registers Reserved area*1 007F FC00h 0080 0000h Peripheral I/O registers Reserved area*1 00F8 0000h 0100 0000h External address space (CS area) 0800 0000h 1000 0000h 0800 0000h 1000 0000h On-chip ROM (program ROM) (write only) 0100 0000h On-chip ROM (data flash) Reserved area*1 FCU-RAM*3 0010 0000h On-chip RAM Reserved area *1 On-chip ROM disabled extended mode 0000 0000h 0001 8000h 0008 0000h Peripheral I/O registers On-chip RAM Reserved area*1 On-chip RAM Reserved area *1 On-chip ROM (data flash) Reserved area*1 FCU-RAM *3 Reserved area*1 Peripheral I/O registers On-chip ROM (program ROM) (write only) External address space (CS area) External address space (SDRAM area) External address space (SDRAM area) Reserved area*1 Reserved area*1 Reserved area*1 FEFF E000h FF00 0000h FF7F C000h FF80 C000h FFF8 0000h FFFF FFFFh On-chip ROM (FCU firmware)*3 (read only) Reserved area*1 On-chip ROM (user boot) (read only) Reserved area *1 FEFF E000h FF00 0000h FF7F C000h FF80 C000h FFF8 0000h FFFF FFFFh On-chip ROM (FCU firmware)*3 (read only) Reserved area*1 On-chip ROM (user boot) (read only) Reserved area*1 On-chip ROM (program ROM) (read only) FF00 0000h External address space On-chip ROM (program ROM) (read only) FFFF FFFFh Notes: 1. Reserved areas should not be accessed, since the correct operation of LSI is not guaranteed if they are accessed. 2. The address space in boot mode and user boot mode is the same as the address space in single-chip mode. 3. For details on the FCU, see section 37, ROM (Flash Memory for Code Storage) and section 38, Data Flash (Flash Memory for Data Storage) in the User's manual: Hardware. Figure 3.1 Memory Map in Each Operating Mode R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 50 of 146 RX62N Group, RX621 Group 3. Address Space 3.2 External Address Space The external address space is classified into CS areas (CS0 to CS7) and SDRAM area (SDCS). The CS area is divided into up to 8 areas (CS0 to CS7), each corresponding to the CSi# signal output from a CSi# (i = 0 to 7) pin. Figure 3.2 shows the address ranges corresponding to the individual CS areas (CS0 to CS7) and SDRAM area (SDCS) in on-chip ROM disabled extended mode. 0000 0000h 0001 8000h 0008 0000h On-chip RAM Reserved area *1 0100 0000h CS7 (16 Mbytes) 01FF FFFFh 0200 0000h CS6 (16 Mbytes) 02FF FFFFh 0300 0000h CS5 (16 Mbytes) 03FF FFFFh 0400 0000h CS4 (16 Mbytes) Peripheral I/O registers 0010 0000h Reserved area*1 0100 0000h External address space (CS area) 04FF FFFFh 0500 0000h CS3 (16 Mbytes) 0800 0000h 1000 0000h External address space (SDRAM area) 05FF FFFFh 0600 0000h CS2 (16 Mbytes) 06FF FFFFh 0700 0000h CS1 (16 Mbytes) 07FF FFFFh 0800 0000h Reserved area*1 SDCS (128 Mbytes) 0FFF FFFFh FF00 0000h External address space*2 (CS area) FFFF FFFFh FF00 0000h CS0 (16 Mbytes) FFFF FFFFh Notes: 1. Reserved areas should not be accessed, since the correct operation of LSI is not guaranteed if they are accessed. 2. The CS0 area is disabled in on-chip ROM enabled extended mode. In this mode, the address space for addresses above 1000 0000h is as shown in figure 4.1. Figure 3.2 Correspondence between External Address Spaces, CS Areas (CS0 to CS7), and SDRAM area (SDCS) (In On-Chip ROM Disabled Extended Mode) R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 51 of 146 RX62N Group, RX621 Group 4. I/O Registers 4. Table 4.1 Address I/O Registers List of I/O Registers (Address Order) (1 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 0000h 0008 0002h 0008 0006h 0008 0008h 0008 000Ch 0008 0010h 0008 0014h 0008 0018h 0008 0020h 0008 0030h 0008 0040h 0008 1300h 0008 1304h 0008 1308h 0008 130Ah 0008 2000h 0008 2004h 0008 2008h 0008 200Ch 0008 2010h 0008 2013h 0008 2014h 0008 2018h 0008 201Ch 0008 201Dh 0008 201Eh 0008 201Fh 0008 2040h 0008 2044h 0008 2048h 0008 204Ch 0008 2050h 0008 2053h 0008 2054h 0008 205Ch 0008 205Dh 0008 205Eh 0008 205Fh 0008 2080h 0008 2084h 0008 2088h SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM BSC BSC BSC BSC DMAC0 DMAC0 DMAC0 DMAC0 DMAC0 DMAC0 DMAC0 DMAC0 DMAC0 DMAC0 DMAC0 DMAC0 DMAC1 DMAC1 DMAC1 DMAC1 DMAC1 DMAC1 DMAC1 DMAC1 DMAC1 DMAC1 DMAC1 DMAC2 DMAC2 DMAC2 Mode monitor register Mode status register System control register 0 System control register 1 Standby control register Module stop control register A Module stop control register B Module stop control register C System clock control register External bus clock control register Oscillation stop detection control register Bus error status clear register Bus error monitoring enable register Bus error status register 1 Bus error status register 2 DMA source address register DMA destination address register DMA transfer count register DMA block transfer count register DMA transfer mode register DMA interrupt setting register DMA address mode register DMA offset register MA transfer enable register DMA software start register DMA status register DMA activation source flag control register DMA source address register DMA destination address register DMA transfer count register DMA block transfer count register DMA transfer mode register DMA interrupt setting register DMA address mode register MA transfer enable register DMA software start register DMA status register DMA activation source flag control register DMA source address register DMA destination address register DMA transfer count register MDMONR MDSR SYSCR0 SYSCR1 SBYCR MSTPCRA MSTPCRB MSTPCRC SCKCR BCKCR OSTDCR BERCLR BEREN BERSR1 BERSR2 DMSAR DMDAR DMCRA DMCRB DMTMD DMINT DMAMD DMOFR DMCNT DMREQ DMSTS DMCSL DMSAR DMDAR DMCRA DMCRB DMTMD DMINT DMAMD DMCNT DMREQ DMSTS DMCSL DMSAR DMDAR DMCRA 16 16 16 16 16 32 32 32 32 8 16 8 8 8 16 32 32 32 16 16 8 16 32 8 8 8 8 32 32 32 16 16 8 16 8 8 8 8 32 32 32 16 16 16 16 16 32 32 32 32 8 16 8 8 8 16 32 32 32 16 16 8 16 32 8 8 8 8 32 32 32 16 16 8 16 8 8 8 8 32 32 32 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 3 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 52 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (2 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 208Ch 0008 2090h 0008 2093h 0008 2094h 0008 209Ch 0008 209Dh 0008 209Eh 0008 209Fh 0008 20C0h 0008 20C4h 0008 20C8h 0008 20CCh 0008 20D0h 0008 20D3h 0008 20D4h 0008 20DCh 0008 20DDh 0008 20DEh 0008 20DFh 0008 2200h 0008 2400h 0008 2404h 0008 2408h 0008 240Ch 0008 240Eh 0008 2800h 0008 2804h 0008 2808h 0008 280Ch 0008 2810h 0008 2812h 0008 2813h 0008 2814h 0008 2818h 0008 281Ch 0008 281Dh 0008 281Eh 0008 2820h 0008 2821h 0008 2822h 0008 2840h 0008 2844h 0008 2848h DMAC2 DMAC2 DMAC2 DMAC2 DMAC2 DMAC2 DMAC2 DMAC2 DMAC3 DMAC3 DMAC3 DMAC3 DMAC3 DMAC3 DMAC3 DMAC3 DMAC3 DMAC3 DMAC3 DMAC DTC DTC DTC DTC DTC EXDMAC0 EXDMAC0 EXDMAC0 EXDMAC0 EXDMAC0 EXDMAC0 EXDMAC0 EXDMAC0 EXDMAC0 EXDMAC0 EXDMAC0 EXDMAC0 EXDMAC0 EXDMAC0 EXDMAC0 EXDMAC1 EXDMAC1 EXDMAC1 DMA block transfer count register DMA transfer mode register DMA interrupt setting register DMA address mode register DMA transfer enable register DMA software start register DMA status register DMA activation source flag control register DMA source address register DMA destination address register DMA transfer count register DMA block transfer count register DMA transfer mode register DMA interrupt setting register DMA address mode register DMA transfer enable register DMA software start register DMA status register DMA activation source flag control register DMACA start register DTC control register DTC vector base register DTC address mode register DTC module start register DTC status register EXDMA source address register EXDMA destination address register EXDMA transfer count register EXDMA block transfer count register EXDMA transfer mode register EXDMA output setting register EXDMA interrupt setting register EXDMA address mode register EXDMA output setting register EXDMA transfer enable register EXDMA software start register EXDMA status register EXDMA external request sense mode register EXDMA external request flag register EXDMA peripheral request flag register EXDMA source address register EXDMA destination address register EXDMA transfer count register DMCRB DMTMD DMINT DMAMD DMCNT DMREQ DMSTS DMCSL DMSAR DMDAR DMCRA DMCRB DMTMD DMINT DMAMD DMCNT DMREQ DMSTS DMCSL DMAST DTCCR DTCVBR DTCADMOD DTCST DTCSTS EDMSAR EDMDAR EDMCRA EDMCRB EDMTMD EDMOMD EDMINT EDMAMD EDMOFR EDMCNT EDMREQ EDMSTS EDMRMD EDMERF EDMPRF EDMSAR EDMDAR EDMCRA 16 16 8 16 8 8 8 8 32 32 32 16 16 8 16 8 8 8 8 8 8 32 8 8 16 32 32 32 16 16 8 8 32 32 8 8 8 8 8 8 32 32 32 16 16 8 16 8 8 8 8 32 32 32 16 16 8 16 8 8 8 8 8 8 32 8 8 16 32 32 32 16 16 8 8 32 32 8 8 8 8 8 8 32 32 32 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 53 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (3 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 284Ch 0008 2850h 0008 2852h 0008 2853h 0008 2854h 0008 285Ch 0008 285Dh 0008 285Eh 0008 2860h 0008 2861h 0008 2862h 0008 2A00h 0008 2BE0h 0008 2BE4h 0008 2BE8h 0008 2BECh 0008 2BF0h 0008 2BF4h 0008 2BF8h 0008 3002h 0008 3004h 0008 3008h 0008 3012h 0008 3014h 0008 3018h 0008 3022h 0008 3024h 0008 3028h 0008 3032h 0008 3034h 0008 3038h 0008 3042h 0008 3044h 0008 3048h 0008 3052h 0008 3054h 0008 3058h 0008 3062h 0008 3064h 0008 3068h 0008 3072h 0008 3074h 0008 3078h 0008 3802h EXDMAC1 EXDMAC1 EXDMAC1 EXDMAC1 EXDMAC1 EXDMAC1 EXDMAC1 EXDMAC1 EXDMAC1 EXDMAC1 EXDMAC1 EXDMAC EXDMAC EXDMAC EXDMAC EXDMAC EXDMAC EXDMAC EXDMAC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC EXDMA block transfer count register EXDMA transfer mode register EXDMA output setting register EXDMA interrupt setting register EXDMA address mode register EXDMA transfer enable register EXDMA software start register EXDMA status register EXDMA external request sense mode register EXDMA external request flag register EXDMA peripheral request flag register EXDMA module start register Cluster buffer register 0 Cluster buffer register 1 Cluster buffer register 2 Cluster buffer register 3 Cluster buffer register 4 Cluster buffer register 5 Cluster buffer register 6 CS0 mode register CS0 wait control register 1 CS0 wait control register 2 CS1 mode register CS1 wait control register 1 CS1 wait control register 2 CS2 mode register CS2 wait control register 1 CS2 wait control register 2 CS3 mode register CS3 wait control register 1 CS3 wait control register 2 CS4 mode register CS4 wait control register 1 CS4 wait control register 2 CS5 mode register CS5 wait control register 1 CS5 wait control register 2 CS6 mode register CS6 wait control register 1 CS6 wait control register 2 CS7 mode register CS7 wait control register 1 CS7 wait control register 2 CS0 control register EDMCRB EDMTMD EDMOMD EDMINT EDMAMD EDMCNT EDMREQ EDMSTS EDMRMD EDMERF EDMPRF EDMAST CLSBR0 CLSBR1 CLSBR2 CLSBR3 CLSBR4 CLSBR5 CLSBR6 CS0MOD CS0WCR1 CS0WCR2 CS1MOD CS1WCR1 CS1WCR2 CS2MOD CS2WCR1 CS2WCR2 CS3MOD CS3WCR1 CS3WCR2 CS4MOD CS4WCR1 CS4WCR2 CS5MOD CS5WCR1 CS5WCR2 CS6MOD CS6WCR1 CS6WCR2 CS7MOD CS7WCR1 CS7WCR2 CS0CR 16 16 8 8 32 8 8 8 8 8 8 8 32 32 32 32 32 32 32 16 32 32 16 32 32 16 32 32 16 32 32 16 32 32 16 32 32 16 32 32 16 32 32 16 16 16 8 8 32 8 8 8 8 8 8 8 32 32 32 32 32 32 32 16 32 32 16 32 32 16 32 32 16 32 32 16 32 32 16 32 32 16 32 32 16 32 32 16 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 54 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (4 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 380Ah 0008 3812h 0008 381Ah 0008 3822h 0008 382Ah 0008 3832h 0008 383Ah 0008 3842h 0008 384Ah 0008 3852h 0008 385Ah 0008 3862h 0008 386Ah 0008 3872h 0008 387Ah 0008 3C00h 0008 3C01h 0008 3C02h 0008 3C10h 0008 3C14h 0008 3C16h 0008 3C20h 0008 3C24h 0008 3C40h 0008 3C44h 0008 3C48h 0008 3C50h 0008 7010h 0008 7015h 0008 7017h 0008 701Bh 0008 701Ch 0008 701Dh 0008 701Eh 0008 701Fh 0008 7020h 0008 7024h 0008 7025h 0008 7026h 0008 7028h 0008 7029h 0008 702Ah 0008 702Ch 0008 702Dh BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC BSC ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU CS0 recovery cycle register CS1 control register CS1 recovery cycle register CS2 control register CS2 recovery cycle register CS3 control register CS3 recovery cycle register CS4 control register CS4 recovery cycle register CS5 control register CS5 recovery cycle register CS6 control register CS6 recovery cycle register CS7 control register CS7 recovery cycle register SDC control register SDC mode register SDRAM access mode register SDRAM self-refresh control register SDRAM refresh control register SDRAM auto-refresh control register SDRAM initialization sequence control register SDRAM initialization register SDRAM address register SDRAM timing register SDRAM mode register SDRAM status register Interrupt request register 016 Interrupt request register 021 Interrupt request register 023 Interrupt request register 027 Interrupt request register 028 Interrupt request register 029 Interrupt request register 030 Interrupt request register 031 Interrupt request register 032 Interrupt request register 036 Interrupt request register 037 Interrupt request register 038 Interrupt request register 040 Interrupt request register 041 Interrupt request register 042 Interrupt request register 044 Interrupt request register 045 CS0REC CS1CR CS1REC CS2CR CS2REC CS3CR CS3REC CS4CR CS4REC CS5CR CS5REC CS6CR CS6REC CS7CR CS7REC SDCCR SDCMOD SDAMOD SDSELF SDRFCR SDRFEN SDICR SDIR SDADR SDTR SDMOD SDSR IR016 IR021 IR023 IR027 IR028 IR029 IR030 IR031 IR032 IR036 IR037 IR038 IR040 IR041 IR042 IR044 IR045 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 16 8 8 16 8 32 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 16 8 8 16 8 32 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 1 to 2 BCLK*10 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 55 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (5 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 702Eh 0008 702Fh 0008 7030h 0008 7031h 0008 7032h 0008 7033h 0008 7038h 0008 7039h 0008 703Ah 0008 703Bh 0008 703Ch 0008 703Eh 0008 703Fh 0008 7040h 0008 7041h 0008 7042h 0008 7043h 0008 7044h 0008 7045h 0008 7046h 0008 7047h 0008 7048h 0008 7049h 0008 704Ah 0008 704Bh 0008 704Ch 0008 704Dh 0008 704Eh 0008 704Fh 0008 705Ah 0008 705Bh 0008 705Ch 0008 7060h 0008 7062h 0008 7063h 0008 7066h 0008 7072h 0008 7073h 0008 7074h 0008 7075h 0008 7076h 0008 7077h 0008 7078h 0008 7079h 0008 707Ah ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU Interrupt request register 046 Interrupt request register 047 Interrupt request register 048 Interrupt request register 049 Interrupt request register 050 Interrupt request register 051 Interrupt request register 056 Interrupt request register 057 Interrupt request register 058 Interrupt request register 059 Interrupt request register 060 Interrupt request register 062 Interrupt request register 063 Interrupt request register 064 Interrupt request register 065 Interrupt request register 066 Interrupt request register 067 Interrupt request register 068 Interrupt request register 069 Interrupt request register 070 Interrupt request register 071 Interrupt request register 072 Interrupt request register 073 Interrupt request register 074 Interrupt request register 075 Interrupt request register 076 Interrupt request register 077 Interrupt request register 078 Interrupt request register 079 Interrupt request register 090 Interrupt request register 091 Interrupt request register 092 Interrupt request register 096 Interrupt request register 098 Interrupt request register 099 Interrupt request register 102 Interrupt request register 114 Interrupt request register 115 Interrupt request register 116 Interrupt request register 117 Interrupt request register 118 Interrupt request register 119 Interrupt request register 120 Interrupt request register 121 Interrupt request register 122 IR046 IR047 IR048 IR049 IR050 IR051 IR056 IR057 IR058 IR059 IR060 IR062 IR063 IR064 IR065 IR066 IR067 IR068 IR069 IR070 IR071 IR072 IR073 IR074 IR075 IR076 IR077 IR078 IR079 IR090 IR091 IR092 IR096 IR098 IR099 IR102 IR114 IR115 IR116 IR117 IR118 IR119 IR120 IR121 IR122 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 56 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (6 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 707Bh 0008 707Ch 0008 707Dh 0008 707Eh 0008 707Fh 0008 7080h 0008 7081h 0008 7082h 0008 7083h 0008 7084h 0008 7085h 0008 7086h 0008 7087h 0008 7088h 0008 7089h 0008 708Ah 0008 708Bh 0008 708Ch 0008 708Dh 0008 708Eh 0008 708Fh 0008 7090h 0008 7091h 0008 7092h 0008 7093h 0008 7094h 0008 7095h 0008 7096h 0008 7097h 0008 7098h 0008 7099h 0008 709Ah 0008 709Bh 0008 709Ch 0008 709Dh 0008 709Eh 0008 709Fh 0008 70A0h 0008 70A1h 0008 70A2h 0008 70A3h 0008 70A4h 0008 70A5h 0008 70A6h 0008 70A7h ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU Interrupt request register 123 Interrupt request register 124 Interrupt request register 125 Interrupt request register 126 Interrupt request register 127 Interrupt request register 128 Interrupt request register 129 Interrupt request register 130 Interrupt request register 131 Interrupt request register 132 Interrupt request register 133 Interrupt request register 134 Interrupt request register 135 Interrupt request register 136 Interrupt request register 137 Interrupt request register 138 Interrupt request register 139 Interrupt request register 140 Interrupt request register 141 Interrupt request register 142 Interrupt request register 143 Interrupt request register 144 Interrupt request register 145 Interrupt request register 146 Interrupt request register 147 Interrupt request register 148 Interrupt request register 149 Interrupt request register 150 Interrupt request register 151 Interrupt request register 152 Interrupt request register 153 Interrupt request register 154 Interrupt request register 155 Interrupt request register 156 Interrupt request register 157 Interrupt request register 158 Interrupt request register 159 Interrupt request register 160 Interrupt request register 161 Interrupt request register 162 Interrupt request register 163 Interrupt request register 164 Interrupt request register 165 Interrupt request register 166 Interrupt request register 167 IR123 IR124 IR125 IR126 IR127 IR128 IR129 IR130 IR131 IR132 IR133 IR134 IR135 IR136 IR137 IR138 IR139 IR140 IR141 IR142 IR143 IR144 IR145 IR146 IR147 IR148 IR149 IR150 IR151 IR152 IR153 IR154 IR155 IR156 IR157 IR158 IR159 IR160 IR161 IR162 IR163 IR164 IR165 IR166 IR167 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 57 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (7 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 70A8h 0008 70A9h 0008 70AAh 0008 70ABh 0008 70ACh 0008 70ADh 0008 70AEh 0008 70AFh 0008 70B0h 0008 70B1h 0008 70B2h 0008 70B3h 0008 70B4h 0008 70B5h 0008 70B6h 0008 70B7h 0008 70B8h 0008 70B9h 0008 70C6h 0008 70C7h 0008 70C8h 0008 70C9h 0008 70CAh 0008 70CBh 0008 70D6h 0008 70D7h 0008 70D8h 0008 70D9h 0008 70DAh 0008 70DBh 0008 70DCh 0008 70DDh 0008 70DEh 0008 70DFh 0008 70E0h 0008 70E1h 0008 70E2h 0008 70E3h 0008 70E4h 0008 70E5h 0008 70EAh 0008 70EBh 0008 70ECh 0008 70EDh 0008 70EEh ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU Interrupt request register 168 Interrupt request register 169 Interrupt request register 170 Interrupt request register 171 Interrupt request register 172 Interrupt request register 173 Interrupt request register 174 Interrupt request register 175 Interrupt request register 176 Interrupt request register 177 Interrupt request register 178 Interrupt request register 179 Interrupt request register 180 Interrupt request register 181 Interrupt request register 182 Interrupt request register 183 Interrupt request register 184 Interrupt request register 185 Interrupt request register 198 Interrupt request register 199 Interrupt request register 200 Interrupt request register 201 Interrupt request register 202 Interrupt request register 203 Interrupt request register 214 Interrupt request register 215 Interrupt request register 216 Interrupt request register 217 Interrupt request register 218 Interrupt request register 219 Interrupt request register 220 Interrupt request register 221 Interrupt request register 222 Interrupt request register 223 Interrupt request register 224 Interrupt request register 225 Interrupt request register 226 Interrupt request register 227 Interrupt request register 228 Interrupt request register 229 Interrupt request register 234 Interrupt request register 235 Interrupt request register 236 Interrupt request register 237 Interrupt request register 238 IR168 IR169 IR170 IR171 IR172 IR173 IR174 IR175 IR176 IR177 IR178 IR179 IR180 IR181 IR182 IR183 IR184 IR185 IR198 IR199 IR200 IR201 IR202 IR203 IR214 IR215 IR216 IR217 IR218 IR219 IR220 IR221 IR222 IR223 IR224 IR225 IR226 IR227 IR228 IR229 IR234 IR235 IR236 IR237 IR238 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 58 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (8 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 70EFh 0008 70F0h 0008 70F1h 0008 70F6h 0008 70F7h 0008 70F8h 0008 70F9h 0008 70FAh 0008 70FBh 0008 70FCh 0008 70FDh 0008 711Bh 0008 711Ch 0008 711Dh 0008 711Eh 0008 711Fh 0008 7124h 0008 7125h 0008 7128h 0008 7129h 0008 712Dh 0008 712Eh 0008 7131h 0008 7132h 0008 7140h 0008 7141h 0008 7142h 0008 7143h 0008 7144h 0008 7145h 0008 7146h 0008 7147h 0008 7148h 0008 7149h 0008 714Ah 0008 714Bh 0008 714Ch 0008 714Dh 0008 714Eh 0008 714Fh 0008 7162h 0008 7163h 0008 7166h 0008 7172h 0008 7173h ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU Interrupt request register 239 Interrupt request register 240 Interrupt request register 241 Interrupt request register 246 Interrupt request register 247 Interrupt request register 248 Interrupt request register 249 Interrupt request register 250 Interrupt request register 251 Interrupt request register 252 Interrupt request register 253 DTC activation enable register 027 DTC activation enable register 028 DTC activation enable register 029 DTC activation enable register 030 DTC activation enable register 031 DTC activation enable register 036 DTC activation enable register 037 DTC activation enable register 040 DTC activation enable register 041 DTC activation enable register 045 DTC activation enable register 046 DTC activation enable register 049 DTC activation enable register 050 DTC activation enable register 064 DTC activation enable register 065 DTC activation enable register 066 DTC activation enable register 067 DTC activation enable register 068 DTC activation enable register 069 DTC activation enable register 070 DTC activation enable register 071 DTC activation enable register 072 DTC activation enable register 073 DTC activation enable register 074 DTC activation enable register 075 DTC activation enable register 076 DTC activation enable register 077 DTC activation enable register 078 DTC activation enable register 079 DTC activation enable register 098 DTC activation enable register 099 DTC activation enable register 102 DTC activation enable register 114 DTC activation enable register 115 IR239 IR240 IR241 IR246 IR247 IR248 IR249 IR250 IR251 IR252 IR253 DTCER027 DTCER028 DTCER029 DTCER030 DTCER031 DTCER036 DTCER037 DTCER040 DTCER041 DTCER045 DTCER046 DTCER049 DTCER050 DTCER064 DTCER065 DTCER066 DTCER067 DTCER068 DTCER069 DTCER070 DTCER071 DTCER072 DTCER073 DTCER074 DTCER075 DTCER076 DTCER077 DTCER078 DTCER079 DTCER098 DTCER099 DTCER102 DTCER114 DTCER115 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 59 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (9 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 7174h 0008 7175h 0008 7179h 0008 717Ah 0008 717Dh 0008 717Eh 0008 7181h 0008 7182h 0008 7183h 0008 7184h 0008 7186h 0008 7187h 0008 7188h 0008 7189h 0008 718Ah 0008 718Bh 0008 718Ch 0008 718Dh 0008 718Eh 0008 718Fh 0008 7190h 0008 7191h 0008 7195h 0008 7196h 0008 7199h 0008 719Ah 0008 719Dh 0008 719Eh 0008 719Fh 0008 71A0h 0008 71A2h 0008 71A3h 0008 71A4h 0008 71A5h 0008 71A6h 0008 71A7h 0008 71A8h 0008 71A9h 0008 71AEh 0008 71AFh 0008 71B1h 0008 71B2h 0008 71B4h 0008 71B5h 0008 71B7h ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU DTC activation enable register 116 DTC activation enable register 117 DTC activation enable register 121 DTC activation enable register 122 DTC activation enable register 125 DTC activation enable register 126 DTC activation enable register 129 DTC activation enable register 130 DTC activation enable register 131 DTC activation enable register 132 DTC activation enable register 134 DTC activation enable register 135 DTC activation enable register 136 DTC activation enable register 137 DTC activation enable register 138 DTC activation enable register 139 DTC activation enable register 140 DTC activation enable register 141 DTC activation enable register 142 DTC activation enable register 143 DTC activation enable register 144 DTC activation enable register 145 DTC activation enable register 149 DTC activation enable register 150 DTC activation enable register 153 DTC activation enable register 154 DTC activation enable register 157 DTC activation enable register 158 DTC activation enable register 159 DTC activation enable register 160 DTC activation enable register 162 DTC activation enable register 163 DTC activation enable register 164 DTC activation enable register 165 DTC activation enable register 166 DTC activation enable register 167 DTC activation enable register 168 DTC activation enable register 169 DTC activation enable register 174 DTC activation enable register 175 DTC activation enable register 177 DTC activation enable register 178 DTC activation enable register 180 DTC activation enable register 181 DTC activation enable register 183 DTCER116 DTCER117 DTCER121 DTCER122 DTCER125 DTCER126 DTCER129 DTCER130 DTCER131 DTCER132 DTCER134 DTCER135 DTCER136 DTCER137 DTCER138 DTCER139 DTCER140 DTCER141 DTCER142 DTCER143 DTCER144 DTCER145 DTCER149 DTCER150 DTCER153 DTCER154 DTCER157 DTCER158 DTCER159 DTCER160 DTCER162 DTCER163 DTCER164 DTCER165 DTCER166 DTCER167 DTCER168 DTCER169 DTCER174 DTCER175 DTCER177 DTCER178 DTCER180 DTCER181 DTCER183 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 60 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (10 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 71B8h 0008 71C6h 0008 71C7h 0008 71C8h 0008 71C9h 0008 71CAh 0008 71CBh 0008 71D7h 0008 71D8h 0008 71DBh 0008 71DCh 0008 71DFh 0008 71E0h 0008 71E3h 0008 71E4h 0008 71EBh 0008 71ECh 0008 71EFh 0008 71F0h 0008 71F7h 0008 71F8h 0008 71FBh 0008 71FCh 0008 7202h 0008 7203h 0008 7204h 0008 7205h 0008 7206h 0008 7207h 0008 7208h 0008 7209h 0008 720Bh 0008 720Ch 0008 720Eh 0008 720Fh 0008 7210h 0008 7211h 0008 7212h 0008 7213h 0008 7214h 0008 7215h 0008 7216h 0008 7217h 0008 7218h 0008 7219h ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU DTC activation enable register 184 DTC activation enable register 198 DTC activation enable register 199 DTC activation enable register 200 DTC activation enable register 201 DTC activation enable register 202 DTC activation enable register 203 DTC activation enable register 215 DTC activation enable register 216 DTC activation enable register 219 DTC activation enable register 220 DTC activation enable register 223 DTC activation enable register 224 DTC activation enable register 227 DTC activation enable register 228 DTC activation enable register 235 DTC activation enable register 236 DTC activation enable register 239 DTC activation enable register 240 DTC activation enable register 247 DTC activation enable register 248 DTC activation enable register 251 DTC activation enable register 252 Interrupt request enable register 02 Interrupt request enable register 03 Interrupt request enable register 04 Interrupt request enable register 05 Interrupt request enable register 06 Interrupt request enable register 07 Interrupt request enable register 08 Interrupt request enable register 09 Interrupt request enable register 0B Interrupt request enable register 0C Interrupt request enable register 0E Interrupt request enable register 0F Interrupt request enable register 10 Interrupt request enable register 11 Interrupt request enable register 12 Interrupt request enable register 13 Interrupt request enable register 14 Interrupt request enable register 15 Interrupt request enable register 16 Interrupt request enable register 17 Interrupt request enable register 18 Interrupt request enable register 19 DTCER184 DTCER198 DTCER199 DTCER200 DTCER201 DTCER202 DTCER203 DTCER215 DTCER216 DTCER219 DTCER220 DTCER223 DTCER224 DTCER227 DTCER228 DTCER235 DTCER236 DTCER239 DTCER240 DTCER247 DTCER248 DTCER251 DTCER252 IER02 IER03 IER04 IER05 IER06 IER07 IER08 IER09 IER0B IER0C IER0E IER0F IER10 IER11 IER12 IER13 IER14 IER15 IER16 IER17 IER18 IER19 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 61 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (11 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 721Ah 0008 721Bh 0008 721Ch 0008 721Dh 0008 721Eh 0008 721Fh 0008 72E0h 0008 72F0h 0008 7300h 0008 7301h 0008 7302h 0008 7303h 0008 7304h 0008 7305h 0008 7306h 0008 7307h 0008 7308h 0008 730Ch 0008 730Dh 0008 730Eh 0008 7310h 0008 7311h 0008 7312h 0008 7314h 0008 7315h 0008 7318h 0008 731Eh 0008 731Fh 0008 7320h 0008 7321h 0008 7322h 0008 7323h 0008 7324h 0008 7325h 0008 7326h 0008 7327h 0008 7328h 0008 7329h 0008 732Ah 0008 732Bh 0008 732Ch 0008 732Dh 0008 732Eh 0008 732Fh 0008 733Ah ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU Interrupt request enable register 1A Interrupt request enable register 1B Interrupt request enable register 1C Interrupt request enable register 1D Interrupt request enable register 1E Interrupt request enable register 1F Software interrupt activation register Fast interrupt set register Interrupt source priority register 00 Interrupt source priority register 01 Interrupt source priority register 02 Interrupt source priority register 03 Interrupt source priority register 04 Interrupt source priority register 05 Interrupt source priority register 06 Interrupt source priority register 07 Interrupt source priority register 08 Interrupt source priority register 0C Interrupt source priority register 0D Interrupt source priority register 0E Interrupt source priority register 10 Interrupt source priority register 11 Interrupt source priority register 12 Interrupt source priority register 14 Interrupt source priority register 15 Interrupt source priority register 18 Interrupt source priority register 1E Interrupt source priority register 1F Interrupt source priority register 20 Interrupt source priority register 21 Interrupt source priority register 22 Interrupt source priority register 23 Interrupt source priority register 24 Interrupt source priority register 25 Interrupt source priority register 26 Interrupt source priority register 27 Interrupt source priority register 28 Interrupt source priority register 29 Interrupt source priority register 2A Interrupt source priority register 2B Interrupt source priority register 2C Interrupt source priority register 2D Interrupt source priority register 2E Interrupt source priority register 2F Interrupt source priority register 3A IER1A IER1B IER1C IER1D IER1E IER1F SWINTR FIR IPR00 IPR01 IPR02 IPR03 IPR04 IPR05 IPR06 IPR07 IPR08 IPR0C IPR0D IPR0E IPR10 IPR11 IPR12 IPR14 IPR15 IPR18 IPR1E IPR1F IPR20 IPR21 IPR22 IPR23 IPR24 IPR25 IPR26 IPR27 IPR28 IPR29 IPR2A IPR2B IPR2C IPR2D IPR2E IPR2F IPR3A 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 62 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (12 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 733Bh 0008 733Ch 0008 7340h 0008 7344h 0008 7345h 0008 7348h 0008 7351h 0008 7352h 0008 7353h 0008 7354h 0008 7355h 0008 7356h 0008 7357h 0008 7358h 0008 7359h 0008 735Ah 0008 735Bh 0008 735Ch 0008 735Dh 0008 735Eh 0008 735Fh 0008 7360h 0008 7361h 0008 7362h 0008 7363h 0008 7364h 0008 7365h 0008 7366h 0008 7367h 0008 7368h 0008 7369h 0008 736Ah 0008 736Bh 0008 7370h 0008 7371h 0008 7372h 0008 7373h 0008 7374h 0008 7375h 0008 7380h 0008 7381h 0008 7382h 0008 7383h 0008 7385h 0008 7386h ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU Interrupt source priority register 3B Interrupt source priority register 3C Interrupt source priority register 40 Interrupt source priority register 44 Interrupt source priority register 45 Interrupt source priority register 48 Interrupt source priority register 51 Interrupt source priority register 52 Interrupt source priority register 53 Interrupt source priority register 54 Interrupt source priority register 55 Interrupt source priority register 56 Interrupt source priority register 57 Interrupt source priority register 58 Interrupt source priority register 59 Interrupt source priority register 5A Interrupt source priority register 5B Interrupt source priority register 5C Interrupt source priority register 5D Interrupt source priority register 5E Interrupt source priority register 5F Interrupt source priority register 60 Interrupt source priority register 61 Interrupt source priority register 62 Interrupt source priority register 63 Interrupt source priority register 64 Interrupt source priority register 65 Interrupt source priority register 66 Interrupt source priority register 67 Interrupt source priority register 68 Interrupt source priority register 69 Interrupt source priority register 6A Interrupt source priority register 6B Interrupt source priority register 70 Interrupt source priority register 71 Interrupt source priority register 72 Interrupt source priority register 73 Interrupt source priority register 74 Interrupt source priority register 75 Interrupt source priority register 80 Interrupt source priority register 81 Interrupt source priority register 82 Interrupt source priority register 83 Interrupt source priority register 85 Interrupt source priority register 86 IPR3B IPR3C IPR40 IPR44 IPR45 IPR48 IPR51 IPR52 IPR53 IPR54 IPR55 IPR56 IPR57 IPR58 IPR59 IPR5A IPR5B IPR5C IPR5D IPR5E IPR5F IPR60 IPR61 IPR62 IPR63 IPR64 IPR65 IPR66 IPR67 IPR68 IPR69 IPR6A IPR6B IPR70 IPR71 IPR72 IPR73 IPR74 IPR75 IPR80 IPR81 IPR82 IPR83 IPR85 IPR86 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 63 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (13 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 7388h 0008 7389h 0008 738Ah 0008 738Bh 0008 738Ch 0008 738Dh 0008 738Eh 0008 738Fh 0008 7400h 0008 7404h 0008 7408h 0008 740Ch 0008 7500h 0008 7501h 0008 7502h 0008 7503h 0008 7504h 0008 7505h 0008 7506h 0008 7507h 0008 7508h 0008 7509h 0008 750Ah 0008 750Bh 0008 750Ch 0008 750Dh 0008 750Eh 0008 750Fh 0008 7580h 0008 7581h 0008 7582h 0008 7583h 0008 8000h 0008 8002h 0008 8004h 0008 8006h 0008 8008h 0008 800Ah 0008 800Ch 0008 8010h 0008 8012h 0008 8014h 0008 8016h 0008 8018h 0008 801Ah ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU ICU CMT CMT0 CMT0 CMT0 CMT1 CMT1 CMT1 CMT CMT2 CMT2 CMT2 CMT3 CMT3 Interrupt source priority register 88 Interrupt source priority register 89 Interrupt source priority register 8A Interrupt source priority register 8B Interrupt source priority register 8C Interrupt source priority register 8D Interrupt source priority register 8E Interrupt source priority register 8F DMACA activation source select register 0 DMACA activation source select register 1 DMACA activation source select register 2 DMACA activation source select register 3 IRQ control register 0 IRQ control register 1 IRQ control register 2 IRQ control register 3 IRQ control register 4 IRQ control register 5 IRQ control register 6 IRQ control register 7 IRQ control register 8 IRQ control register 9 IRQ control register 10 IRQ control register 11 IRQ control register 12 IRQ control register 13 IRQ control register 14 IRQ control register 15 Non-maskable interrupt status register Non-maskable interrupt enable register Non-maskable interrupt clear register NMI pin interrupt control register Compare match timer start register 0 Compare match timer control register Compare match timer counter Compare match timer constant register Compare match timer control register Compare match timer counter Compare match timer constant register Compare match timer start register 1 Compare match timer control register Compare match timer counter Compare match timer constant register Compare match timer control register Compare match timer counter IPR88 IPR89 IPR8A IPR8B IPR8C IPR8D IPR8E IPR8F DMRSR0 DMRSR1 DMRSR2 DMRSR3 IRQCR0 IRQCR1 IRQCR2 IRQCR3 IRQCR4 IRQCR5 IRQCR6 IRQCR7 IRQCR8 IRQCR9 IRQCR10 IRQCR11 IRQCR12 IRQCR13 IRQCR14 IRQCR15 NMISR NMIER NMICLR NMICR CMSTR0 CMCR CMCNT CMCOR CMCR CMCNT CMCOR CMSTR1 CMCR CMCNT CMCOR CMCR CMCNT 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 ICLK 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 64 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (14 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 801Ch 0008 8028h 0008 8028h 0008 8029h 0008 802Ah 0008 802Bh 0008 8030h 0008 8032h 0008 8034h 0008 8040h 0008 8042h 0008 8044h 0008 8046h 0008 8050h 0008 8051h 0008 8052h 0008 8053h 0008 805Fh 0008 8060h 0008 8062h 0008 8064h 0008 8066h 0008 8070h 0008 8071h 0008 8072h 0008 8073h 0008 807Fh 0008 80C0h 0008 80C2h 0008 80C4h 0008 80C5h 0008 81E6h 0008 81E7h 0008 81E8h 0008 81E9h 0008 81EAh 0008 81EBh 0008 81ECh*1 0008 81EDh*2 CMT3 WDT WDT WDT WDT WDT IWDT IWDT IWDT AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD0 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 AD1 DA DA DA DA PPG0 PPG0 PPG0 PPG0 PPG0 PPG0 PPG0 PPG0 PPG0 PPG0 PPG1 PPG1 PPG1 Compare match timer constant register Timer control/status register Write window A register Timer counter Write window B register Reset control/status register IWDT refresh register IWDT control register IWDT status register A/D data register A A/D data register B A/D data register C A/D data register D A/D control/status register A/D control register ADDRn format select register A/D sampling state register A/D self-diagnostic register A/D data register A A/D data register B A/D data register C A/D data register D A/D control/status register A/D control register ADDRn format select register A/D sampling state register A/D self-diagnostic register D/A data register 0 D/A data register 1 D/A control register DADRm format select register PPG output control register PPG output mode register Next data enable register H Next data enable register L Output data register H Output data register L Next data register H Next data register L Next data register H2 Next data register L2 PPG trigger select register PPG output control register PPG output mode register CMCOR READ.TCSR WRITE.WINA READ.TCNT WRITE.WINB READ.RSTC SR IWDTRR IWDTCR IWDTSR ADDRA ADDRB ADDRC ADDRD ADCSR ADCR ADDPR ADSSTR ADDIAGR ADDRA ADDRB ADDRC ADDRD ADCSR ADCR ADDPR ADSSTR ADDIAGR DADR0 DADR1 DACR DADPR PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL NDRH2 NDRL2 PTRSLR PCR PMR 16 8 16 8 16 8 8 16 16 16 16 16 16 8 8 8 8 8 16 16 16 16 8 8 8 8 8 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 16 8 16 8 8 16 16 16 16 16 16 8 8 8 8 8 16 16 16 16 8 8 8 8 8 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 0008 81EEh*1 0008 81EFh*2 0008 81F0h 0008 81F6h 0008 81F7h R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 65 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (15 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 81F8h 0008 81F9h 0008 81FAh 0008 81FBh 0008 81FCh*3 0008 81FDh*4 PPG1 PPG1 PPG1 PPG1 PPG1 PPG1 PPG1 PPG1 TMR0 TMR1 TMR0 TMR1 TMR0 TMR1 TMR0 TMR1 TMR0 TMR1 TMR0 TMR1 TMR01 TMR01 TMR01 TMR01 TMR2 TMR3 TMR2 TMR3 TMR2 TMR3 TMR2 TMR3 TMR2 TMR3 TMR2 TMR3 TMR2 TMR2 TMR2 TMR2 SCI0 SCI0 SCI0 SCI0 SCI0 Next data enable register H Next data enable register L Output data register H Output data register L Next data register H Next data register L Next data register H2 Next data register L2 Timer control register Timer control register Timer control/status register Timer control/status register Time constant register A Time constant register A Time constant register B Time constant register B Timer counter Timer counter Timer counter control register Timer counter control register Time constant register A Time constant register B Timer counter Timer counter control register Timer control register Timer control register Timer control/status register Timer control/status register Time constant register A Time constant register A Time constant register B Time constant register B Timer counter Timer counter Timer counter control register Timer counter control register Time constant register A Time constant register B Timer counter Timer counter control register Serial mode register Bit rate register Serial control register Transmit data register Serial status register NDERH NDERL PODRH PODRL NDRH NDRL NDRH2 NDRL2 TCR TCR TCSR TCSR TCORA TCORA TCORB TCORB TCNT TCNT TCCR TCCR TCORA TCORB TCNT TCCR TCR TCR TCSR TCSR TCORA TCORA TCORB TCORB TCNT TCNT TCCR TCCR TCORA TCORB TCNT TCCR SMR BRR SCR TDR SSR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 8 8 8 8 8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 0008 81FEh*3 0008 81FFh*4 0008 8200h 0008 8201h 0008 8202h 0008 8203h 0008 8204h 0008 8205h 0008 8206h 0008 8207h 0008 8208h 0008 8209h 0008 820Ah 0008 820Bh 0008 8204h 0008 8206h 0008 8208h 0008 820Ah 0008 8210h 0008 8211h 0008 8212h 0008 8213h 0008 8214h 0008 8215h 0008 8216h 0008 8217h 0008 8218h 0008 8219h 0008 821Ah 0008 821Bh 0008 8214h 0008 8216h 0008 8218h 0008 821Ah 0008 8240h 0008 8241h 0008 8242h 0008 8243h 0008 8244h R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 66 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (16 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 8245h 0008 8246h 0008 8247h 0008 8240h 0008 8241h 0008 8242h 0008 8243h 0008 8244h 0008 8245h 0008 8246h 0008 8248h 0008 8249h 0008 824Ah 0008 824Bh 0008 824Ch 0008 824Dh 0008 824Eh 0008 824Fh 0008 8248h 0008 8249h 0008 824Ah 0008 824Bh 0008 824Ch 0008 824Dh 0008 824Eh 0008 8250h 0008 8251h 0008 8252h 0008 8253h 0008 8254h 0008 8255h 0008 8256h 0008 8257h 0008 8250h 0008 8251h 0008 8252h 0008 8253h 0008 8254h 0008 8255h 0008 8256h 0008 8258h 0008 8259h 0008 825Ah 0008 825Bh 0008 825Ch SCI0 SCI0 SCI0 SMCI0 SMCI0 SMCI0 SMCI0 SMCI0 SMCI0 SMCI0 SCI1 SCI1 SCI1 SCI1 SCI1 SCI1 SCI1 SCI1 SMCI1 SMCI1 SMCI1 SMCI1 SMCI1 SMCI1 SMCI1 SCI2 SCI2 SCI2 SCI2 SCI2 SCI2 SCI2 SCI2 SMCI2 SMCI2 SMCI2 SMCI2 SMCI2 SMCI2 SMCI2 SCI3 SCI3 SCI3 SCI3 SCI3 Receive data register Smart card mode register Serial extended mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial extended mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial extended mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register RDR SCMR SEMR SMR BRR SCR TDR SSR RDR SCMR SMR BRR SCR TDR SSR RDR SCMR SEMR SMR BRR SCR TDR SSR RDR SCMR SMR BRR SCR TDR SSR RDR SCMR SEMR SMR BRR SCR TDR SSR RDR SCMR SMR BRR SCR TDR SSR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 67 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (17 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 825Dh 0008 825Eh 0008 825Fh 0008 8258h 0008 8259h 0008 825Ah 0008 825Bh 0008 825Ch 0008 825Dh 0008 825Eh 0008 8268h 0008 8269h 0008 826Ah 0008 826Bh 0008 826Ch 0008 826Dh 0008 826Eh 0008 826Fh 0008 8268h 0008 8269h 0008 826Ah 0008 826Bh 0008 826Ch 0008 826Dh 0008 826Eh 0008 8270h 0008 8271h 0008 8272h 0008 8273h 0008 8274h 0008 8275h 0008 8276h 0008 8277h 0008 8270h 0008 8271h 0008 8272h 0008 8273h 0008 8274h 0008 8275h 0008 8276h 0008 8280h 0008 8281h 0008 8282h 0008 8300h 0008 8301h SCI3 SCI3 SCI3 SMCI3 SMCI3 SMCI3 SMCI3 SMCI3 SMCI3 SMCI3 SCI5 SCI5 SCI5 SCI5 SCI5 SCI5 SCI5 SCI5 SMCI5 SMCI5 SMCI5 SMCI5 SMCI5 SMCI5 SMCI5 SCI6 SCI6 SCI6 SCI6 SCI6 SCI6 SCI6 SCI6 SMCI6 SMCI6 SMCI6 SMCI6 SMCI6 SMCI6 SMCI6 CRC CRC CRC RIIC0 RIIC0 Receive data register Smart card mode register Serial extended mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register SMCI3 Receive data register SMCI3 Smart card mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial extended mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial extended mode register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register CRC control register CRC data input register CRC data output register I 2C bus control register 1 RDR SCMR SEMR SMR BRR SCR TDR SSR RDR SCMR SMR BRR SCR TDR SSR RDR SCMR SEMR SMR BRR SCR TDR SSR RDR SCMR SMR BRR SCR TDR SSR RDR SCMR SEMR SMR BRR SCR TDR SSR RDR SCMR CRCCR CRCDIR CRCDOR ICCR1 ICCR2 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 I2C bus control register 2 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 68 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (18 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 8302h 0008 8303h 0008 8304h 0008 8305h 0008 8306h 0008 8307h 0008 8308h 0008 8309h 0008 830Ah 0008 830Bh 0008 830Ch 0008 830Dh 0008 830Eh 0008 830Fh 0008 8310h 0008 8311h 0008 8312h 0008 8313h 0008 8320h 0008 8321h 0008 8322h 0008 8323h 0008 8324h 0008 8325h 0008 8326h 0008 8327h 0008 8328h 0008 8329h 0008 832Ah 0008 832Bh 0008 832Ch 0008 832Dh 0008 832Eh 0008 832Fh 0008 8330h 0008 8331h 0008 8332h 0008 8333h 0008 8380h 0008 8381h 0008 8382h 0008 8383h 0008 8384h 0008 8388h 0008 8389h RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC0 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RIIC1 RSPI0 RSPI0 RSPI0 RSPI0 RSPI0 RSPI0 RSPI0 I2C bus mode register 1 I2C bus mode register 2 I2C bus mode register 3 I 2C bus function enable register ICMR1 ICMR2 ICMR3 ICFER ICSER ICIER ICSR1 ICSR2 SARL0 SARU0 SARL1 SARU1 SARL2 SARU2 ICBRL ICBRH ICDRT ICDRR ICCR1 ICCR2 ICMR1 ICMR2 ICMR3 ICFER ICSER ICIER ICSR1 ICSR2 SARL0 SARU0 SARL1 SARU1 SARL2 SARU2 ICBRL ICBRH ICDRT ICDRR SPCR SSLP SPPCR SPSR SPDR SPSCR SPSSR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 32 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16, 32 8 8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 I2C bus status enable register I 2C bus interrupt enable register I2C bus status register 1 I2C bus status register 2 Slave address register L0 Slave address register U0 Slave address register L1 Slave address register U1 Slave address register L2 Slave address register U2 I 2C bus bit rate low-level register I2C bus bit rate high-level register I2C bus transmit data register I 2C bus receive data register I2C bus control register 1 I2C bus control register 2 I 2C bus mode register 1 I2C bus mode register 2 I2C bus mode register 3 I 2C bus function enable register I2C bus status enable register I2C bus interrupt enable register I 2C bus status register 1 I2C bus status register 2 Slave address register L0 Slave address register U0 Slave address register L1 Slave address register U1 Slave address register L2 Slave address register U2 I 2C bus bit rate low-level register I2C bus bit rate high-level register I2C bus transmit data register I 2C bus receive data register RSPI control register RSPI slave select polarity register RSPI pin control register RSPI status register RSPI data register RSPI sequence control register RSPI sequence status register R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 69 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (19 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 838Ah 0008 838Bh 0008 838Ch 0008 838Dh 0008 838Eh 0008 838Fh 0008 8390h 0008 8392h 0008 8394h 0008 8396h 0008 8398h 0008 839Ah 0008 839Ch 0008 839Eh 0008 83A0h 0008 83A1h 0008 83A2h 0008 83A3h 0008 83A4h 0008 83A8h 0008 83A9h 0008 83AAh 0008 83ABh 0008 83ACh 0008 83ADh 0008 83AEh 0008 83AFh 0008 83B0h 0008 83B2h 0008 83B4h 0008 83B6h 0008 83B8h 0008 83BAh 0008 83BCh 0008 83BEh 0008 8600h 0008 8601h 0008 8602h 0008 8603h 0008 8604h 0008 8605h 0008 8606h 0008 8607h 0008 8608h 0008 8609h RSPI0 RSPI0 RSPI0 RSPI0 RSPI0 RSPI0 RSPI0 RSPI0 RSPI0 RSPI0 RSPI0 RSPI0 RSPI0 RSPI0 RSPI1 RSPI1 RSPI1 RSPI1 RSPI1 RSPI1 RSPI1 RSPI1 RSPI1 RSPI1 RSPI1 RSPI1 RSPI1 RSPI1 RSPI1 RSPI1 RSPI1 RSPI1 RSPI1 RSPI1 RSPI1 MTU3 MTU4 MTU3 MTU4 MTU3 MTU3 MTU4 MTU4 MTU3 MTU4 RSPI bit rate register RSPI data control register RSPI clock delay register SPBR SPDCR SPCKD 8 8 8 8 8 8 16 16 16 16 16 16 16 16 8 8 8 8 16, 32 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 8 8 8 8 16, 32 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 RSPI slave select negation delay register SSLND RSPI next-access delay register RSPI control register 2 RSPI command register 0 RSPI command register 1 RSPI command register 2 RSPI command register 3 RSPI command register 4 RSPI command register 5 RSPI command register 6 RSPI command register 7 RSPI control register RSPI slave select polarity register RSPI pin control register RSPI status register RSPI data register RSPI sequence control register RSPI sequence status register RSPI bit rate register RSPI data control register RSPI clock delay register SPND SPCR2 SPCMD0 SPCMD1 SPCMD2 SPCMD3 SPCMD4 SPCMD5 SPCMD6 SPCMD7 SPCR SSLP SPPCR SPSR SPDR SPSCR SPSSR SPBR SPDCR SPCKD RSPI slave select negation delay register SSLND RSPI next-access delay register RSPI control register 2 RSPI command register 0 RSPI command register 1 RSPI command register 2 RSPI command register 3 RSPI command register 4 RSPI command register 5 RSPI command register 6 RSPI command register 7 Timer control register Timer control register Timer mode register Timer mode register Timer I/O control register H Timer I/O control register L Timer I/O control register H Timer I/O control register L Timer interrupt enable register Timer interrupt enable register SPND SPCR2 SPCMD0 SPCMD1 SPCMD2 SPCMD3 SPCMD4 SPCMD5 SPCMD6 SPCMD7 TCR TCR TMDR TMDR TIORH TIORL TIORH TIORL TIER TIER R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 70 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (20 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 860Ah 0008 860Dh 0008 860Eh 0008 860Fh 0008 8610h 0008 8612h 0008 8614h 0008 8616h 0008 8618h 0008 861Ah 0008 861Ch 0008 861Eh 0008 8620h 0008 8622h 0008 8624h 0008 8626h 0008 8628h 0008 862Ah 0008 862Ch 0008 862Dh 0008 8630h 0008 8631h 0008 8632h 0008 8634h 0008 8636h 0008 8638h 0008 8639h 0008 8640h 0008 8644h 0008 8646h 0008 8648h 0008 864Ah 0008 8660h 0008 8680h 0008 8681h 0008 8684h 0008 8700h 0008 8701h 0008 8702h 0008 8703h MTUA MTUA MTUA MTUA MTU3 MTU4 MTUA MTUA MTU3 MTU3 MTU4 MTU4 MTUA MTUA MTU3 MTU3 MTU4 MTU4 MTU3 MTU4 MTUA MTUA MTUA MTUA MTUA MTU3 MTU4 MTU4 MTU4 MTU4 MTU4 MTU4 MTUA MTUA MTUA MTUA MTU0 MTU0 MTU0 MTU0 Timer output master enable register Timer gate control register Timer output control register 1 Timer output control register 2 Timer counter Timer counter Timer cycle data register Timer dead time data register Timer general register A Timer general register B Timer general register A Timer general register B Timer subcounter Timer cycle buffer register Timer general register C Timer general register D Timer general register C Timer general register D Timer status register Timer status register Timer waveform control register Timer start register TITCNT Timer buffer transfer set register Timer dead time enable register Timer output level buffer register Timer buffer operation transfer mode register Timer buffer operation transfer mode register Timer A/D converter start request control register Timer A/D converter start request cycle set register A Timer A/D converter start request cycle set register B Timer A/D converter start request cycle set buffer register A Timer A/D converter start request cycle set buffer register B Timer waveform control register Timer start register Timer synchronous register Timer read/write enable register Timer control register Timer mode register Timer I/O control register H Timer I/O control register L TOER TGCR TOCR1 TOCR2 TCNT TCNT TCDR TCDR TGRA TGRB TGRA TGRB TCNTS TCBR TGRC TGRD TGRC TGRD TSR TSR TITCR TITCNT TBTER TDER TOLBR TBTM TBTM TADCR TADCORA TADCORB TADCOBRA TADCOBRB TWCR TSTR TSYR TRWER TCR TMDR TIORH TIORL 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 8 8 8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 71 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (21 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 8704h 0008 8705h 0008 8706h 0008 8708h 0008 870Ah 0008 870Ch 0008 870Eh 0008 8720h 0008 8722h 0008 8724h 0008 8726h 0008 8780h 0008 8781h 0008 8782h 0008 8784h 0008 8785h 0008 8786h 0008 8788h 0008 878Ah 0008 8790h 0008 8800h 0008 8801h 0008 8802h 0008 8804h 0008 8805h 0008 8806h 0008 8808h 0008 880Ah 0008 8880h 0008 8882h 0008 8884h 0008 8886h 0008 8890h 0008 8892h 0008 8894h 0008 8896h 0008 88A0h 0008 88A2h 0008 88A4h 0008 88A6h 0008 88B2h 0008 88B4h 0008 88B6h MTU0 MTU0 MTU0 MTU0 MTU0 MTU0 MTU0 MTU0 MTU0 MTU0 MTU0 MTU1 MTU1 MTU1 MTU1 MTU1 MTU1 MTU1 MTU1 MTU1 MTU2 MTU2 MTU2 MTU2 MTU2 MTU2 MTU2 MTU2 MTU5 MTU5 MTU5 MTU5 MTU5 MTU5 MTU5 MTU5 MTU5 MTU5 MTU5 MTU5 MTU5 MTU5 MTU5 Timer interrupt enable register Timer status register Timer counter Timer general register A Timer general register B Timer general register C Timer general register D Timer general register E Timer general register F Timer interrupt enable register 2 Timer buffer operation transfer mode register Timer control register Timer mode register Timer I/O control register Timer interrupt enable register Timer status register Timer counter Timer general register A Timer general register B Timer input capture control register Timer control register Timer mode register Timer I/O control register Timer interrupt enable register Timer status register Timer counter Timer general register A Timer general register B Timer counter U Timer general register U Timer control register U Timer I/O control register U Timer counter V Timer general register V Timer control register V Timer I/O control register V Timer counter W Timer general register W Timer control register W Timer I/O control register W Timer interrupt enable register Timer start register Timer compare match clear register TIER TSR TCNT TGRA TGRB TGRC TGRD TGRE TGRF TIER2 TBTM TCR TMDR TIOR TIER TSR TCNT TGRA TGRB TICCR TCR TMDR TIOR TIER TSR TCNT TGRA TGRB TCNTU TGRU TCRU TIORU TCNTV TGRV TCRV TIORV TCNTW TGRW TCRW TIORW TIER TSTR TCNTCMPCL R 8 8 16 16 16 16 16 16 16 8 8 8 8 8 8 8 16 16 16 8 8 8 8 8 8 16 16 16 16 16 8 8 16 16 8 8 16 16 16 8 8 8 8 8 8 16 16 16 16 16 16 16 8 8 8 8 8 8 8 16 16 16 8 8 8 8 8 8 16 16 16 16 16 8 8 16 16 8 8 16 16 8 8 8 8 8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 72 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (22 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 8900h 0008 8902h 0008 8904h 0008 8906h 0008 8908h 0008 890Ah 0008 890Bh 0008 890Ch 0008 890Eh 0008 8A00h 0008 8A01h 0008 8A02h 0008 8A03h 0008 8A04h 0008 8A05h 0008 8A06h 0008 8A07h 0008 8A08h 0008 8A09h 0008 8A0Ah 0008 8A0Dh 0008 8A0Eh 0008 8A0Fh 0008 8A10h 0008 8A12h 0008 8A14h 0008 8A16h 0008 8A18h 0008 8A1Ah 0008 8A1Ch 0008 8A1Eh 0008 8A20h 0008 8A22h 0008 8A24h 0008 8A26h 0008 8A28h 0008 8A2Ah 0008 8A2Ch 0008 8A2Dh 0008 8A30h 0008 8A31h 0008 8A32h 0008 8A34h 0008 8A36h POE POE POE POE POE POE POE POE POE MTU9 MTU10 MTU9 MTU10 MTU9 MTU9 MTU10 MTU10 MTU9 MTU10 MTUB MTUB MTUB MTUB MTU9 MTU10 MTUB MTUB MTU9 MTU9 MTU10 MTU10 MTUB MTUB MTU9 MTU9 MTU10 MTU10 MTU9 MTU10 MTUB MTUB MTUB MTUB MTUB Input level control/status register 1 Output level control/status register 1 Input level control/status register 2 Output level control/status register 2 Input level control/status register 3 Software port output enable register Port output enable control register 1 Port output enable control register 2 Input level control/status register 4 Timer control register Timer control register Timer mode register Timer mode register Timer I/O control register H Timer I/O control register L Timer I/O control register H Timer I/O control register L Timer interrupt enable register Timer interrupt enable register Timer output master enable register Timer gate control register Timer output control register 1 Timer output control register 2 Timer counter Timer counter Timer cycle data register Timer dead time data register Timer general register A Timer general register B Timer general register A Timer general register B Timer subcounter MTUB Timer cycle buffer register Timer general register C Timer general register D Timer general register C Timer general register D Timer status register Timer status register Timer interrupt skipping set register Timer interrupt skipping counter TUB Timer dead time enable register Timer dead time enable register Timer output level buffer register ICSR1 OCSR1 ICSR2 OCSR2 ICSR3 SPOER POECR1 POECR2 ICSR4 TCR TCR TMDR TMDR TIORH TIORL TIORH TIORL TIER TIER TOER TGCR TOCR1 TOCR2 TCNT TCNT TCDR TDDR TGRA TGRB TGRA TGRB TCNTS TCBR TGRC TGRD TGRC TGRD TSR TSR TITCR TITCNT TBTER TDER TOLBR 16 16 16 16 16 8 8 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 16 16 16 16 16 8 8 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 73 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (23 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 8A38h 0008 8A39h 0008 8A40h 0008 8A44h 0008 8A46h 0008 8A48h 0008 8A4Ah 0008 8A60h 0008 8A80h 0008 8A81h 0008 8A84h 0008 8B00h 0008 8B01h 0008 8B02h 0008 8B03h 0008 8B04h 0008 8B05h 0008 8B06h 0008 8B08h 0008 8B0Ah 0008 8B0Ch 0008 8B0Eh 0008 8B20h 0008 8B22h 0008 8B24h 0008 8B26h 0008 8B80h 0008 8B81h 0008 8B82h 0008 8B84h 0008 8B85h 0008 8B86h 0008 8B88h 0008 8B8Ah 0008 8B90h 0008 8C00h 0008 8C01h 0008 8C02h 0008 8C04h MTU9 MTU10 MTU10 MTU10 MTU10 MTU10 MTU10 MTUB MTUB MTUB MTUB MTU6 MTU6 MTU6 MTU6 MTU6 MTU6 MTU6 MTU6 MTU6 MTU6 MTU6 MTU6 MTU6 MTU6 MTU6 MTU7 MTU7 MTU7 MTU7 MTU7 MTU7 MTU7 MTU7 MTU7 MTU8 MTU8 MTU8 MTU8 Timer buffer operation transfer mode register Timer buffer operation transfer mode register Timer A/D converter start request control register Timer A/D converter start request cycle set register A Timer A/D converter start request cycle set register B Timer A/D converter start request cycle set buffer register A Timer A/D converter start request cycle set buffer register B Timer waveform control register Timer start register MTUB Timer synchronous register MTUB Timer read/write enable register Timer control register Timer mode register Timer I/O control register H Timer I/O control register L Timer interrupt enable register Timer status register Timer counter Timer general register A Timer general register B Timer general register C Timer general register D Timer general register E Timer general register F Timer interrupt enable register 2 Timer buffer operation transfer mode register Timer control register Timer mode register Timer I/O control register Timer interrupt enable register Timer status register Timer counter Timer general register A Timer general register B Timer input capture control register Timer control register Timer mode register Timer I/O control register Timer interrupt enable register TBTM TBTM TADCR TADCORA TADCORB TADCOBRA TADCOBRB TWCR TSTR TSYR TRWER TCR TMDR TIORH TIORL TIER TSR TCNT TGRA TGRB TGRC TGRD TGRE TGRF TIER2 TBTM TCR TMDR TIOR TIER TSR TCNT TGRA TGRB TICCR TCR TMDR TIOR TIER 8 8 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 8 8 8 8 8 8 8 16 16 16 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 8 8 8 8 8 8 8 16 16 16 8 8 8 8 8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 74 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (24 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 8C05h 0008 8C06h 0008 8C08h 0008 8C0Ah 0008 8C80h 0008 8C82h 0008 8C84h 0008 8C86h 0008 8C90h 0008 8C92h 0008 8C94h 0008 8C96h 0008 8CA0h 0008 8CA2h 0008 8CA4h 0008 8CA6h 0008 8CB2h 0008 8CB4h 0008 8CB6h 0008 9000h 0008 9004h 0008 9008h 0008 900Ch 0008 900Eh 0008 9010h 0008 9020h 0008 9022h 0008 9024h 0008 9026h 0008 9028h 0008 902Ah 0008 902Ch 0008 902Eh 0008 C000h 0008 C001h 0008 C002h 0008 C003h 0008 C004h 0008 C005h 0008 C006h 0008 C007h 0008 C008h 0008 C009h MTU8 MTU8 MTU8 MTU8 MTU11 MTU11 MTU11 MTU11 MTU11 MTU11 MTU11 MTU11 MTU11 MTU11 MTU11 MTU11 MTU11 MTU11 MTU11 S12AD S12AD S12AD S12AD S12AD S12AD S12AD S12AD S12AD S12AD S12AD S12AD S12AD S12AD PORT0 PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT7 PORT8 PORT9 Timer status register Timer counter Timer general register A Timer general register B Timer counter U Timer general register U Timer control register U Timer I/O control register U Timer counter V Timer general register V Timer control register V Timer I/O control register V Timer counter W Timer general register W Timer control register W Timer I/O control register W Timer interrupt enable register Timer start register Timer compare match clear register A/D control register A/D channel select register A/D-converted value addition mode select register A/D-converted value addition count select register A/D control extended register A/D start trigger select register A/D data register 0 A/D data register 1 A/D data register 2 A/D data register 3 A/D data register 4 A/D data register 5 A/D data register 6 A/D data register 7 Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register TSR TCNT TGRA TGRB TCNTU TGRU TCRU TIORU TCNTV TGRV TCRV TIORV TCNTW TGRW TCRW TIORW TIER TSTR 8 16 16 16 16 16 8 8 16 16 8 8 16 16 8 8 8 8 8 16 16 16 16 16 8 8 16 16 8 8 16 16 8 8 8 8 8 8 16 16 8 16 8 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 TCNTCMPCLR 8 ADCSR ADANS ADADS ADADC ADCER ADSTRGR ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 DDR DDR DDR DDR DDR DDR DDR*6*7 DDR*6*7 DDR*6*7 DDR*6*7 8 16 16 8 16 8 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 75 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (25 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 C00Ah 0008 C00Bh 0008 C00Ch 0008 C00Dh 0008 C00Eh 0008 C00Fh 0008 C010h 0008 C020h 0008 C021h 0008 C022h 0008 C023h 0008 C024h 0008 C025h 0008 C026h 0008 C027h 0008 C028h 0008 C029h 0008 C02Ah 0008 C02Bh 0008 C02Ch 0008 C02Dh 0008 C02Eh 0008 C02Fh 0008 C030h 0008 C040h 0008 C041h 0008 C042h 0008 C043h 0008 C044h 0008 C045h 0008 C046h 0008 C047h 0008 C048h 0008 C049h 0008 C04Ah 0008 C04Bh 0008 C04Ch 0008 C04Dh 0008 C04Eh 0008 C04Fh 0008 C050h 0008 C060h 0008 C061h 0008 C062h 0008 C063h PORTA PORTB PORTC PORTD PORTE PORTF PORTG PORT0 PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT7 PORT8 PORT9 PORTA PORTB PORTC PORTD PORTE PORTF PORTG PORT0 PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT7 PORT8 PORT9 PORTA PORTB PORTC PORTD PORTE PORTF PORTG PORT0 PORT1 PORT2 PORT3 Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data direction register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Data register Port register Port register Port register Port register Port register Port register Port register Port register Port register Port register Port register Port register Port register Port register Port register Port register Port register Input buffer control register Input buffer control register Input buffer control register Input buffer control register DDR DDR DDR DDR DDR*7 DDR*5*6*7 DDR*5*6*7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 DR DR DR DR DR DR DR*6*7 DR*6*7 DR*6*7 DR*6*7 DR DR DR DR DR*7 DR*5*6*7 DR**5*6*7 PORT PORT PORT PORT PORT PORT PORT*6*7 PORT*6*7 PORT*6*7 PORT*6*7 PORT PORT PORT PORT PORT*7 PORT*5*6*7 PORT*5*6*7 ICR ICR ICR ICR R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 76 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (26 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 C064h 0008 C065h 0008 C066h 0008 C067h 0008 C068h 0008 C069h 0008 C06Ah 0008 C06Bh 0008 C06Ch 0008 C06Dh 0008 C06Eh 0008 C06Fh 0008 C070h 0008 C080h 0008 C081h 0008 C082h 0008 C083h 0008 C08Ch 0008 C0C9h 0008 C0CAh 0008 C0CBh 0008 C0CCh 0008 C0CDh 0008 C0CEh 0008 C0D0h 0008 C100h 0008 C101h 0008 C102h 0008 C103h 0008 C104h 0008 C105h 0008 C106h 0008 C107h 0008 C108h 0008 C109h 0008 C10Ah 0008 C10Bh 0008 C10Ch 0008 C10Dh 0008 C10Eh 0008 C10Fh 0008 C110h 0008 C111h 0008 C113h 0008 C114h PORT4 PORT5 PORT6 PORT7 PORT8 PORT9 PORTA PORTB PORTC PORTD PORTE PORTF PORTG PORT0 PORT1 PORT2 PORT3 PORTC PORT9 PORTA PORTB PORTC PORTD PORTE PORTG IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT IOPORT Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Input buffer control register Open drain control register Open drain control register Open drain control register Open drain control register Open drain control register Pull-up resistor control register Pull-up resistor control register Pull-up resistor control register Pull-up resistor control register Pull-up resistor control register Pull-up resistor control register Pull-up resistor control register Port function register 0 Port function register 1 Port function register 2 Port function register 3 Port function register 4 Port function register 5 Port function register 6 Port function register 7 Port function register 8 Port function register 9 Port function register A Port function register B Port function register C Port function register D Port function register E Port function register F Port function register G Port function register H Port function register J Port function register K ICR ICR ICR*6*7 ICR*6*7 ICR*6*7 ICR*6*7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 ICR ICR ICR ICR ICR*7 ICR*5*6*7 ICR*5*6*7 ODR ODR ODR ODR ODR PCR*6*7 PCR PCR PCR PCR PCR*7 PCR*5*6*7 PF0CSE PF1CSS*6*7 PF2CSS*6*7 PF3BUS PF4BUS PF5BUS PF6BUS PF7DMA PF8IRQ PF9IRQ PFAADC PFBTMR PFCMTU PFDMTU PFENET PFFSCI PFGSPI PFHSPI PFJCAN PFKUSB R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 77 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (27 / 35) Module Abbreviation Register Name Register Abbreviation PFLUSB*6*7 PFMPOE*7 PFNPOE*7 Number of Bits Access Size Number of Access Cycles 0008 C115h 0008 C116h 0008 C117h 0008 C280h 0008 C281h 0008 C282h 0008 C283h 0008 C284h 0008 C285h 0008 C289h 0008 C28Ah 0008 C28C 0008 C28Dh 0008 C290h 0008 C291h 0008 C292h 0008 C293h 0008 C294h 0008 C295h 0008 C296h 0008 C297h 0008 C298h 0008 C299h 0008 C29Ah 0008 C29Bh 0008 C29Ch 0008 C29Dh 0008 C29Eh 0008 C29Fh 0008 C2A0h 0008 C2A1h 0008 C2A2h 0008 C2A3h 0008 C2A4h 0008 C2A5h 0008 C2A6h 0008 C2A7h 0008 C2A8h 0008 C2A9h 0008 C2AAh 0008 C2ABh 0008 C2ACh 0008 C2ADh 0008 C2AEh IOPORT IOPORT IOPORT SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM FLASH SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM Port function register L Port function register M Port function register N Deep standby control register Deep standby wait control register Deep standby interrupt enable register Deep standby interrupt flag register Deep standby interrupt edge register Reset status register Flash write erase protection register Sub-clock oscillator control register Key code register for voltage detection control register Voltage detection control register Deep standby backup register 0 Deep standby backup register 1 Deep standby backup register 2 Deep standby backup register 3 Deep standby backup register 4 Deep standby backup register 5 Deep standby backup register 6 Deep standby backup register 7 Deep standby backup register 8 Deep standby backup register 9 Deep standby backup register 10 Deep standby backup register 11 Deep standby backup register 12 Deep standby backup register 13 Deep standby backup register 14 Deep standby backup register 15 Deep standby backup register 16 Deep standby backup register 17 Deep standby backup register 18 Deep standby backup register 19 Deep standby backup register 20 Deep standby backup register 21 Deep standby backup register 22 Deep standby backup register 23 Deep standby backup register 24 Deep standby backup register 25 Deep standby backup register 26 Deep standby backup register 27 Deep standby backup register 28 Deep standby backup register 29 Deep standby backup register 30 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 4 to 5 PCLK*8 DPSBYCR DPSWCR DPSIER DPSIFR DPSIEGR RSTSR FWEPROR SUBOSCCR LVDKEYR LVDCR DPSBKR0 DPSBKR1 DPSBKR2 DPSBKR3 DPSBKR4 DPSBKR5 DPSBKR6 DPSBKR7 DPSBKR8 DPSBKR9 DPSBKR10 DPSBKR11 DPSBKR12 DPSBKR13 DPSBKR14 DPSBKR15 DPSBKR16 DPSBKR17 DPSBKR18 DPSBKR19 DPSBKR20 DPSBKR21 DPSBKR22 DPSBKR23 DPSBKR24 DPSBKR25 DPSBKR26 DPSBKR27 DPSBKR28 DPSBKR29 DPSBKR30 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 78 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (28 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0008 C2AFh 0008 C400h 0008 C402h 0008 C404h 0008 C406h 0008 C408h 0008 C40Ah 0008 C40Ch 0008 C40Eh 0008 C410h 0008 C412h 0008 C414h 0008 C416h 0008 C418h 0008 C41Ah 0008 C41Ch 0008 C41Eh 0008 C422h 0008 C424h 0009 0200h to 0009 03FFh 0009 0400h 0009 0404h 0009 0408h 0009 040Ch 0009 0410h 0009 0414h 0009 0418h 0009 041Ch 0009 0420h 0009 0424h 0009 0428h 0009 042Ch 0009 0820h to 0009 083Fh 0009 0840h 0009 0842h 0009 0844h 0009 0848h 0009 0849h 0009 084Ah 0009 084Bh 0009 084Ch 0009 084Dh 0009 084Eh SYSTEM RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC RTC CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 Deep standby backup register 31 64-Hz counter Second counter Minute counter Hour counter Day-of-week counter Date counter Month counter Year counter Second alarm register Minute alarm register Hour alarm register Day-of-week alarm register Date alarm register Month alarm register Year alarm register Year alarm enable register RTC control register 1 RTC control register 2 Mailbox registers 0 to 31 Mask register 0 Mask register 1 Mask register 2 Mask register 3 Mask register 4 Mask register 5 Mask register 6 Mask register 7 FIFO received ID compare register 0 FIFO received ID compare register 1 Mask invalid register Mailbox interrupt enable register Message control registers 0 to 31 Control register Status register Bit configuration register Receive FIFO control register Receive FIFO pointer control register Transmit FIFO control register Transmit FIFO pointer control register Error interrupt enable register Error interrupt factor judge register Receive error count register DPSBKR31 R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR RYRAR RYRAREN RCR1 RCR2 MB0 to MB031 MKR0 MKR1 MKR2 MKR3 MKR4 MKR5 MKR6 MKR7 FIDCR0 FIDCR1 MKIVLR MIER C0MCTL0 to C0MCTL031 CTLR STR BCR RFCR RFPCR TFCR TFPCR EIER EIFR RECR 8 8 8 8 8 8 8 8 16 8 8 8 8 8 8 16 8 8 8 128 32 32 32 32 32 32 32 32 32 32 32 32 8 16 16 32 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 8 8 8 8 16 8 8 8 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32 8 8, 16 8, 16 8, 16, 32 8 8 8 8 8 8 8 4 to 5 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 79 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (29 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 0009 084Fh 0009 0850h 0009 0851h 0009 0852h 0009 0853h 0009 0854h 0009 0856h 0009 0858h 000A 0000h 000A 0004h 000A 0008h 000A 0014h 000A 0018h 000A 001Ch 000A 0020h 000A 0022h 000A 0028h 000A 002Ah 000A 002Ch 000A 002Eh 000A 0030h 000A 0032h 000A 0036h 000A 0038h 000A 003Ah 000A 003Ch 000A 0040h 000A 0042h 000A 0046h 000A 0048h 000A 004Ah 000A 004Ch 000A 004Eh 000A 0050h CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 CAN0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 Transmit error count register Error code store register Channel search support register Mailbox search status registe Mailbox search mode registe Time stamp registerr Acceptance filter support register Test control register System configuration control register System configuration status register 0 Device state control register 0 CFIFO port register D0FIFO port register D1FIFO port register CFIFO port select register CFIFO port control register D0FIFO port select register D0FIFO port control register D1FIFO port select register D1FIFO port control register Interrupt enable register 0 Interrupt enable register 1 BRDY interrupt enable register NRDY interrupt enable register BEMP interrupt enable register SOF output configuration register Interrupt status register 0 Interrupt status register 1 BRDY interrupt enable register NRDY interrupt status register BEMP interrupt status register Frame number register Device state change register USB address register TECR ECSR CSSR MSSR MSMR TSR AFSR TCR SYSCFG SYSSTS0 DVSTCTR0 CFIFO D0FIFO D1FIFO CFIFOSEL CFIFOCTR D0FIFOSEL D0FIFOCTR D1FIFOSEL D1FIFOCTR INTENB0 INTENB1 BRDYENB NRDYENB BEMPENB SOFCFG INTSTS0 INTSTS1 BRDYSTS NRDYSTS BEMPSTS FRMNUM DVCHGR USBADDR 8 8 8 8 8 16 16 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8, 16 8, 16 8 16 16 16 8, 16 8, 16 8, 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 3 to 4 PCLK*8 at least 9 PCLK*9 at least 9 PCLK*9 3 to 4 PCLK*8 3 to 4 PCLK*8 3 to 4 PCLK*8 3 to 4 PCLK*8 3 to 4 PCLK*8 3 to 4 PCLK*8 3 to 4 PCLK*8 3 to 4 PCLK*8 3 to 4 PCLK*8 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 80 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (30 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 000A 0054h 000A 0056h 000A 0058h 000A 005Ah 000A 005Ch 000A 005Eh 000A 0060h 000A 0064h 000A 0068h 000A 006Ch 000A 006Eh 000A 0070h 000A 0072h 000A 0074h 000A 0076h 000A 0078h 000A 007Ah 000A 007Ch 000A 007Eh 000A 0080h 000A 0090h 000A 0092h 000A 0094h 000A 0096h 000A 0098h 000A 009Ah USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB request type register USB request value register USB request index register USB request length register DCP configuration register DCP maximum packet size register DCP control register Pipe window select register Pipe configuration register Pipe maximum packet size register Pipe cycle control register Pipe 1 control register Pipe 2 control register Pipe 3 control register Pipe 4 control register Pipe 5 control register Pipe 6 control register Pipe 7 control register Pipe 8 control register Pipe 9 control register Pipe 1 transaction counter enable register Pipe 1 transaction counter register Pipe 2 transaction counter enable register Pipe 2 transaction counter register Pipe 3 transaction counter enable register Pipe 3 transaction counter register USBREQ USBVAL USBINDX USBLENG DCPCFG DCPMAXP DCPCTR PIPESEL PIPECFG PIPEMAXP PIPEPERI PIPE1CTR PIPE2CTR PIPE3CTR PIPE4CTR PIPE5CTR PIPE6CTR PIPE7CTR PIPE8CTR PIPE9CTR PIPE1TRE PIPE1TRN PIPE2TRE PIPE2TRN PIPE3TRE PIPE3TRN 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 81 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (31 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 000A 009Ch 000A 009Eh 000A 00A0h 000A 00A2h 000A 00D0h 000A 00D2h 000A 00D4h 000A 00D6h 000A 00D8h 000A 00DAh 000A 0200h 000A 0204h 000A 0208h 000A 0214h 000A 0218h 000A 021Ch 000A 0220h 000A 0222h 000A 0228h 000A 022Ah 000A 022Ch 000A 022Eh 000A 0230h 000A 0232h 000A 0236h 000A 0238h 000A 023Ah 000A 023Ch 000A 0240h 000A 0242h USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB0 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 Pipe 4 transaction counter enable register Pipe 4 transaction counter register Pipe 5 transaction counter enable register Pipe 5 transaction counter register Device address 0 configuration register Device address 1 configuration register Device address 2 configuration register Device address 3 configuration register Device address 4 configuration register Device address 5 configuration register System configuration control register System configuration status register 0 Device state control register 0 CFIFO port register D0FIFO port register D1FIFO port register CFIFO port select register CFIFO port control register D0FIFO port select register D0FIFO port control register D1FIFO port select register D1FIFO port control register Interrupt enable register 0 Interrupt enable register 1 BRDY interrupt enable register NRDY interrupt enable register BEMP interrupt enable register SOF output configuration register Interrupt status register 0 Interrupt status register 1 PIPE4TRE PIPE4TRN PIPE5TRE PIPE5TRN DEVADD0 DEVADD1 DEVADD2 DEVADD3 DEVADD4 DEVADD5 SYSCFG SYSSTS0 DVSTCTR0 CFIFO D0FIFO D1FIFO CFIFOSEL CFIFOCTR D0FIFOSEL D0FIFOCTR D1FIFOSEL D1FIFOCTR INTENB0 INTENB1 BRDYENB NRDYENB BEMPENB SOFCFG INTSTS0 INTSTS1 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8, 16 8, 16 8, 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 3 to 4 PCLK*8 at least 9 PCLK*9 at least 9 PCLK*9 3 to 4 PCLK*8 3 to 4 PCLK*8 3 to 4 PCLK*8 3 to 4 PCLK*8 3 to 4 PCLK*8 3 to 4 PCLK*8 3 to 4 PCLK*8 3 to 4 PCLK*8 3 to 4 PCLK*8 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 82 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (32 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 000A 0246h 000A 0248h 000A 024Ah 000A 024Ch 000A 024Eh 000A 0250h 000A 0254h 000A 0256h 000A 0258h 000A 025Ah 000A 025Ch 000A 025Eh 000A 0260h 000A 0264h 000A 0268h 000A 026Ch 000A 026Eh 000A 0270h 000A 0272h 000A 0274h 000A 0276h 000A 0278h 000A 027Ah 000A 027Ch 000A 027Eh 000A 0280h USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 BRDY interrupt status register NRDY interrupt status register BEMP interrupt status register Frame number register Device state change register USB address register USB request type register USB request value register USB request index register USB request length register DCP configuration register DCP maximum packet size register DCP control register Pipe window select register Pipe configuration register Pipe maximum packet size register Pipe cycle control register Pipe 1 control register Pipe 2 control register Pipe 3 control register Pipe 4 control register Pipe 5 control register Pipe 6 control register Pipe 7 control register Pipe 8 control register Pipe 9 control register BRDYSTS NRDYSTS BEMPSTS FRMNUM DVCHGR USBADDR USBREQ USBVAL USBINDX USBLENG DCPCFG DCPMAXP DCPCTR PIPESEL PIPECFG PIPEMAXP PIPEPERI PIPE1CTR PIPE2CTR PIPE3CTR PIPE4CTR PIPE5CTR PIPE6CTR PIPE7CTR PIPE8CTR PIPE9CTR 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 83 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (33 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 000A 0290h 000A 0292h 000A 0294h 000A 0296h 000A 0298h 000A 029Ah 000A 029Ch 000A 029Eh 000A 02A0h 000A 02A2h 000A 02D0h 000A 02D2h 000A 02D4h 000A 02D6h 000A 02D8h 000A 02DAh 000A 0400h 000A 0404h 000C 0000h 000C 0008h 000C 0010h 000C 0018h 000C 0020h 000C 0028h 000C 0030h 000C 0038h 000C 0040h 000C 0048h 000C 0050h 000C 0058h USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB1 USB USB EDMAC EDMAC EDMAC EDMAC EDMAC EDMAC EDMAC EDMAC EDMAC EDMAC EDMAC EDMAC Pipe 1 transaction counter enable register Pipe 1 transaction counter register Pipe 2 transaction counter enable register Pipe 2 transaction counter register Pipe 3 transaction counter enable register Pipe 3 transaction counter register Pipe 4 transaction counter enable register Pipe 4 transaction counter register Pipe 5 transaction counter enable register Pipe 5 transaction counter register Device address 0 configuration register Device address 1 configuration register Device address 2 configuration register Device address 3 configuration register Device address 4 configuration register Device address 5 configuration register Deep standby USB transceiver control/ pin monitor register Deep standby USB suspend/resume interrupt register EDMAC mode register EDMAC transmit request register EDMAC receive request register Transmit descriptor list start address register Receive descriptor list start address register ETHERC/EDMAC status register ETHERC/EDMAC status interrupt permission register Transmit/receive status copy enable register Receive missed-frame counter register Transmit FIFO threshold register FIFO depth register Receiving method control register PIPE1TRE PIPE1TRN PIPE2TRE PIPE2TRN PIPE3TRE PIPE3TRN PIPE4TRE PIPE4TRN PIPE5TRE PIPE5TRN DEVADD0 DEVADD1 DEVADD2 DEVADD3 DEVADD4 DEVADD5 DPUSR0R DPUSR1R EDMR EDTRR EDRRR TDLAR RDLAR EESR EESIPR TRSCER RMFCR TFTR FDR RMCR 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 32 32 32 32 32 32 32 32 32 32 32 32 32 32 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 at least 9 PCLK*9 1 to 2PCLK*8 1 to 2PCLK*8 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 84 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (34 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 000C 0064h 000C 0068h 000C 006Ch 000C 0070h 000C 0078h 000C 007Ch 000C 00C8h 000C 00CCh 000C 00D4h 000C 00D8h 000C 0100h 000C 0108h 000C 0110h 000C 0118h 000C 0120h 000C 0128h 000C 0140h 000C 0150h 000C 0154h 000C 0158h 000C 0160h 000C 0164h 000C 0168h 000C 016Ch 000C 01C0h 000C 01C8h 000C 01D0h 000C 01D4h 000C 01D8h 000C 01DCh 000C 01E4h 000C 01E8h 000C 01ECh 000C 01F0h 000C 01F4h 000C 01F8h 007F C402h 007F C410h EDMAC EDMAC EDMAC EDMAC EDMAC EDMAC EDMAC EDMAC EDMAC EDMAC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC ETHERC FLASH FLASH Transmit FIFO underrun counter Receive FIFO overflow counter Independent output signal setting register Flow control start FIFO threshold setting register Receive data padding insert register Transmit interrupt setting register Receive buffer write address register TFUCR RFOCR IOSR FCFTR RPADIR TRIMD RBWAR 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 8 8 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 8 8 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 4 to 5 ICLK 2 to 3 PCLK*8 2 to 3 PCLK*8 Receive descriptor fetch address register RDFAR Transmit buffer read address register Transmit descriptor fetch address register ETHERC mode register Receive frame length register ETHERC status register ETHERC interrupt enable register PHY interface register PHY status register Random number generation counter upper limit setting register IPG register Automatic PAUSE frame register Manual PAUSE frame register PAUSE frame receive counter register Automatic PAUSE frame retransmit count register PAUSE frame retransmit counter register Broadcast frame receive count setting register MAC address high register MAC address low register Transmit retry over counter register Delayed collision detect counter register Lost carrier counter register Carrier not detect counter register TBRAR TDFAR ECMR RFLR ECSR ECSIPR PIR PSR RDMLR IPGR APR MPR RFCF TPAUSER TPAUSECR BCFRR MAHR MALR TROCR CDCR LCCR CNDCR CRC error frame receive counter register CEFCR Frame receive error counter register Too-short frame receive counter register Too-long frame receive counter register Residual-bit frame receive counter register Multicast address frame receive counter register Flash mode register Flash access status register FRECR TSFRCR TLFRCR RFCR MAFCR FMODR FASTAT R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 85 of 146 RX62N Group, RX621 Group Table 4.1 Address 4. I/O Registers List of I/O Registers (Address Order) (35 / 35) Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles 007F C411h 007F C412h 007F C440h 007F C442h 007F C450h 007F C452h 007F C454h 007F FFB0h 007F FFB1h 007F FFB2h 007F FFB4h 007F FFB6h 007F FFBAh 007F FFC8h 007F FFCAh 007F FFCCh 007F FFCEh 007F FFE8h FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH FLASH Flash access error interrupt enable register Flash ready interrupt enable register Data flash read enable register0 Data flash read enable register1 Data flash programming/erasure enable register0 Data flash programming/erasure enable register1 FCU RAM enable register Flash status register 0 Flash status register 1 Flash P/E mode entry register Flash protect register Flash reset register FCU command register FCU processing switching register Data flash blank check control register Flash P/E status register Data flash blank check status register Peripheral clock notification register FAEINT FRDYIE DFLRE0 DFLRE1 DFLWE0 DFLWE1 FCURAME FSTATR0 FSTATR1 FENTRYR FPROTR FRESETR FCMDR FCPSR DFLBCCNT FPESTAT DFLBCSTAT PCKAR 8 8 16 16 16 16 16 8 8 16 16 16 16 16 16 16 16 16 8 8 16 16 16 16 16 8 8 16 16 16 16 16 16 16 16 16 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 2 to 3 PCLK*8 Note 1. When the same output trigger is specified for pulse output groups 2 and 3 by the PPG0.PCR setting, the PPG0.NDRH address is 000881ECh. When different output triggers are specified, the PPG0.NDRH2 addresses for pulse output groups 2 and 3 are 000881EEh and 000881ECh, respectively. Note 2. When the same output trigger is specified for pulse output groups 0 and 1 by the PPG0.PCR setting, the PPG0.NDRL address is 000881EDh. When different output triggers are specified, the PPG0.NDRL2 addresses for pulse output groups 0 and 1 are 000881EFh and 000881EDh, respectively. Note 3. When the same output trigger is specified for pulse output groups 6 and 7 by the PPG1.PCR setting, the PPG1.NDRH address is 000881FCh. When different output triggers are specified, the PPG1.NDRH2 addresses for pulse output groups 6 and 7 are 000881FEh and 000881FCh, respectively. Note 4. When the same output trigger is specified for pulse output groups 4 and 5 by the PPG1.PCR setting, the PPG1.NDRL address is 000881FDh. When different output triggers are specified, the PPG1.NDRL2 addresses for pulse output groups 4 and 5 are 000881FFh and 000881FDh, respectively. Note 5. This register is not supported by the 145-pin TFLGA or 144-pin LQFP version. Note 6. This register is not supported by the 100-pin LQFP version. Note 7. This register is not supported by the 85-pin TFLGA version. Note 8. The number of access states depends on the number of divided cycles for clock synchronization (0 to 1 PCLK, 0 to 1 BCLK). Note 9. Access may be disabled if a register is accessed during the USB operation. R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 86 of 146 RX62N RX621 5. Electrical Characteristics 5. 5.1 Table 5.1 Item Electrical Characteristics Absolute Maximum Ratings Absolute Maximum Ratings Symbol VCC PLLVCC VCC_USB VIN Value -0.3 to +4.6 Unit V Power supply voltage Input voltage (except for ports 00 to 02, 07, ports 12, 13, 16, 17, ports 20, 21, port 33) Input voltage (ports 00 to 02, 07, ports 12, 13, 16, 17, ports 20, 21, port 33*1) Reference power supply voltage Analog power supply voltage Analog input voltage Operating temperature Storage temperature -0.3 to VCC+0.3 V VIN -0.3 to +5.8 V VREF AVCC*2 VAN Topr Tstg -0.3 to VCC+0.3 -0.3 to +4.6 -0.3 to VCC+0.3 -40 to +85 -55 to +125 V V V C C Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded. Note 1. Ports 00 to 02, 07, ports 12, 13, 16, 17, ports 20, 21, and port 33 are 5 V tolerant. Note 2. Connect AVCC to VCC. When neither the A/D converter nor the D/A converter is in use, do not leave the AVCC, VREFH, AVSS, and VREFL pins open. Connect the AVCC and VREFH pins to VCC, and the AVSS and VREFL pins to VSS, respectively. R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 87 of 1931 RX62N RX621 5. Electrical Characteristics 5.2 Table 5.2 DC Characteristics DC Characteristics (1) Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V Ta = -40 to +85C Item Schmitt trigger input voltage*2 IRQ input MTU input pin*1 TMR input pin*1 SCI input pin*1 ADTRG input pin*1 RES#, NMI RIIC input pin (except for SMBus) pin*1 Symbol VIH VIL VT Min. VCC x 0.8 -0.3 VCC x 0.06 Typ. -- -- -- Max. VCC+0.3 VCC x 0.2 -- Unit V Test Conditions VIH VIL VT VCC x 0.7 -0.3 VCC x 0.05 VCC x 0.8 -0.3 -- -- -- -- -- 5.8 VCC x 0.3 -- 5.8 VCC x 0.2 Ports 00 to 02, 07 ports 12, 13, 16, 17 ports 20, 21 port 33 Ports 03, 05, 10, 11, 14, 15 ports 22 to 27 ports 30 to 32, 34, 35 ports 4 to G Other input pins Input high voltage (except Schmitt trigger input pin) MD pin, EMLE EXTAL, RSPI, ETHERC EXDMAC, WAIT#, TCK XCIN D0 to D31 RIIC (SMBus) Input low voltage (except Schmitt trigger input pin) MD pin, EMLE EXTAL, RSPI, ETHERC EXDMAC, WAIT#, TCK XCIN D0 to D31 RIIC (SMBus) VIH VIL VIH VIL VCC x 0.8 -0.3 -- -- VCC+0.3 VCC x 0.2 VIH VCC x 0.9 VCC x 0.8 VCC x 0.8 VCC x 0.7 2.1 -- -- -- -- -- -- -- -- -- -- VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC+0.3 VCC x 0.1 VCC x 0.2 VCCx0.2 VCCx0.3 0.8 V VIL -0.3 -0.3 -0.3 -0.3 -0.3 V R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 88 of 1931 RX62N RX621 5. Electrical Characteristics Table 5.3 DC Characteristics (2) Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V Ta = -40 to +85C Item Output high voltage Output low voltage All output pins All output pins (except for RIIC pins) RIIC pins Symbol VOH VOL Min. VCC-0.5 -- -- -- RIIC pins (only P12 and P13 in channel 0) VOL -- -- Input leakage current Three-state leakage current (off state) RES#, MD pin, EMLE, NMI | Iin | | ITSI | -- Typ. -- -- -- -- -- 0.4 -- Max. -- 0.5 0.4 0.6 0.4 -- 1.0 A V Unit V V V Test Conditions IOH = -1mA IOL = 1.0mA IOL = 3.0mA IOL = 6.0mA IOL = 15.0mA (ICFER.FMPE = 1) IOL = 20.0mA (ICFER.FMPE = 1) Vin = 0V Vin = VCC Vin = 0V Vin = VCC Ports 03, 05, 10, 11, 14, 15 ports 22 to 27 ports 30 to 32, 34, 35 ports 4 to G Ports 00 to 02, 07, 12, 13 Ports 16, 17, 20, 21, 33 -- -- 1.0 A -- -Ip Cin 10 -- -- -- -- 5.0 300 15 A pF VCC = 2.7 to 3.6V Vin = 0V Vin = 0V f = 1MHz Ta = 25C Input pull-up MOS current Input capacitance Ports 9 to E, G All input pins (except for ports 12, 13, 20, 21 ports 40 to 47, and EMLE) Ports 12, 13, 20, 21, Ports 40 to 47, EMLE -- -- 30 R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 89 of 1931 RX62N RX621 5. Electrical Characteristics Table 5.4 DC Characteristics (3) Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V Ta = -40 to +85C Item Supply current*2 In operation Max.*3 Peripheral function: Clocks supplied*5 Peripheral function Clocks not supplied*5 Sleep All-module-clock-stop Standby mode mode*7 Symbol ICC *4 Min. -- -- -- -- -- -- Typ. -- 48 15 20 14 0.12 30 Max. 100 -- -- 60 28 3.0 206 Unit mA Test Conditions ICLK = 100MHz PCLK = 50MHz BCLK = 50MHz Software standby mode Deep software standby mode RTC in operation RAM, USB retained RAM, USB power supply halted RTC halted RAM, USB retained RAM, USB power supply halted mA A -- -- 26 66 A -- 25 200 A -- 21 60 A Analog power supply current During 12-bit A/D conversion (per unit) During 10-bit A/D conversion (per unit) During D/A conversion (per unit) Idle (all units) AICC -- -- -- -- 2.5 0.8 0.3 30 0.5 0.06 0.6 0.4 -- -- 3.0 1.2 2.0 35 0.7 0.1 1.0 0.6 -- 20 mA mA A A mA mA mA mA V ms/V Reference power supply current During 12-bit A/D conversion (per unit) During 10-bit A/D conversion (per unit) During D/A conversion (per unit) Idle (all units) AICC -- -- -- -- RAM standby voltage VCC rising gradient VRAM SVCC 2.48 -- Note 1. This does not include the pins, which are multiplexed as ports 00 to 02, 07, ports 12, 13, 16, 17, ports 20, 21, and port 33 for 5 V tolerant. Note 2. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state. Note 3. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation. Note 4. ICC depends on f (ICLK) as follows. (ICLK: PCLK: BCLK = 8 : 4: 2) ICC max. = 0.89 x f + 11 (max.) ICC typ. = 0.43 x f + 5 (normal operation, peripheral function: clocks supplied) ICC typ. = 0.30 x f + 5 (normal operation, peripheral function: clocks not supplied) ICC max. = 0.48 x f + 12 (sleep mode) Note 5. This does not include the BGO operation. Note 6. Incremented if data is written to or erased from the ROM or data flash for data storage during the program execution. Note 7. The values are for reference. R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 90 of 1931 RX62N RX621 5. Electrical Characteristics Table 5.5 Permissible Output Currents Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V Ta = -40 to +85C Item Permissible output low current (average value per pin) All output pins except for RIIC pins RIIC pins (ICFER.FMPE = 0) RIIC pins (ICFER.FMPE = 1) Permissible output low current (max. value per pin) All output pins except for RIIC pins RIIC pins (ICFER.FMPE = 0) RIIC pins (ICFER.FMPE = 1) Permissible output low current (total) Permissible output high current (average value per pin) Total of all output pins All output pins (except for USB_DPUPE pin) USB_DPUPE pin Permissible output high current (max. value per pin) Permissible output high current (total) All output pins Total of all output pins Symbol IOL IOL IOL IOL IOL IOL IOL -IOH Min. -- Typ. -- Max. 2.0 Unit mA mA mA mA mA mA mA mA -- -- -- -- -- -- 6.0 20.0 4.0 -- -- -- -- -- -- -- -- 6.0 20.0 80 2.0 -IOH -IOH -IOH -- -- -- -- -- -- 3.0 4.0 80 mA mA mA Caution: To protect the LSI's reliability, the output current values should not exceed the permissible output current. R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 91 of 1931 RX62N RX621 5. Electrical Characteristics 5.3 Table 5.6 AC Characteristics Operation Frequency Value [176-pin LFBGA/145-pin TFLGA/144-pin LQFP] Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V ICLK = 8 to 100MHz, PCLK = 8 to 50MHz, BCLK = 8 to 100MHz, SDCLK = 8 to 50MHz Ta = -40 to +85C Item Operation frequency System clock (ICLK) Peripheral module clock (PCLK) External bus clock (BCLK) BCLK pin output SDRAM clock (SDCLK) SDCLK pin output Symbol f Min. 8*1 8*2 8 8 8 8 Typ. -- -- -- -- -- -- Max. 100 50 100 50 50 50 Unit MHz Note 1. Note 1:The ICLK must run at a frequency of at least 12.5 MHz if the Ethernet controller is in use. Note 2. Note 2:The PCLK must run at a frequency of at least 24 MHz if the USB is in use. Table 5.7 Operation Frequency Value [100-pin LQFP/85-pin TFLGA] Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V ICLK = 8 to 100MHz, PCLK = 8 to 50MHz, BCLK = 8 to 50MHz Ta = -40 to +85C Item Operation frequency System clock (ICLK) Peripheral module clock (PCLK) External bus clock (BCLK) BCLK pin output Symbol f Min. 8*1 8*2 8 8 Typ. -- -- -- -- Max. 100 50 50 25 Unit MHz Note 1. The ICLK must run at a frequency of at least 12.5 MHz if the Ethernet controller is in use. Note 2. The PCLK must run at a frequency of at least 24 MHz if the USB is in use. R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 92 of 1931 RX62N RX621 5. Electrical Characteristics 5.3.1 Table 5.8 Clock Timing Clock Timing Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V Ta = -40 to +85C Item BCLK pin output cycle time [176-pin LFBGA/145-pin TFLGA/144-pin LQFP] BCLK pin output cycle time [100-pin LQFP/85-pin TFLGA] BCLK pin output high pulse width BCLK pin output low pulse width BCLK pin output rising time BCLK pin output falling time SDCLK pin output cycle time SDCLK pin output high pulse width SDCLK pin output low pulse width SDCLK pin output rising time SDCLK pin output falling time Oscillation settling time after reset (crystal) Oscillation settling time after leaving software standby mode (crystal) Oscillation settling time after leaving deep software standby mode (crystal) EXTAL external clock output delay settling time EXTAL external clock input low pulse width EXTAL external clock input high pulse width EXTAL external clock rising time EXTAL external clock falling time XCIN sub-clock oscillation settling time XCIN sub-clock oscillation frequency On-chip oscillator (IWDTCLK) oscillation frequency Symbol tBcyc tBcyc tCH tCL tCr tCf tSDcyc tCH tCL tCr tCf tOSC1 tOSC2 tOSC3 tDEXT tEXL tEXH tEXr tEXf tSUBOSC fSUB fIWDTCLK Min. 20 40 5 5 -- -- 20 5 5 -- -- 10 10 10 1 35.71 35.71 -- -- 2 32.768 62.5 Max. 125 125 -- -- 5 5 125 -- -- 5 5 -- -- -- -- -- -- 5 5 -- -- 187.5 Unit ns ns ns ns ns ns ns ns ns ns ns ms ms ms ms ns ns ns ns s kHz kHz Figure 5.6 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.2 Figure 5.5 Test Conditions Figure 5.1 R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 93 of 1931 RX62N RX621 5. Electrical Characteristics tBcyc, tSDcyc tCH tCf BCLK pin output, SDCLK pin output tCL tCr Test conditions: VOH = VCC x 0.7, VOL = VCC x 0.3, IOH = -1.0mA, IOL = 1.0mA, C = 30pF Figure 5.1 BCLK Pin Output, SDCLK Pin Output Timing EXTAL VCC tDEXT tOSC1 RES# ICLK Figure 5.2 Oscillation Settling Timing Oscillator ICLK IRQ IRQCRn.IRQMD[1:0] 01 10 SSBY IRQ exception handling IRQMD[1:0] = 10b SSBY = 1 WAIT instruction Software standby mode (power-down mode) Oscillation settling time tOSC2 IRQ exception handling Figure 5.3 Oscillation Settling Timing after Software Standby Mode R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 94 of 1931 RX62N RX621 5. Electrical Characteristics Oscillator ICLK IRQ Invalid by the internal reset Set IRQ interrupt DIRQnF set request DIRQnEG bit Set DPSBY bit When IOKEEP=H Set IOKEEP bit L Operating L Set H Cleared I/O port When IOKEEP=L Retained Operating IOKEEP bit I/O port Operating Retained Operating DPSRSTF flag Internal reset IRQ exception handling DIRQnEG = 1 SSBY = 1 Deep software standby mode (power-down mode) Oscillation settling time tOSC3 Reset exception handling WAIT instruction Figure 5.4 Oscillation Settling Timing after Deep Software Standby Mode R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 95 of 1931 RX62N RX621 5. Electrical Characteristics tEXH tEXL EXTAL tEXr tEXf VCCx0.5 Figure 5.5 EXTAL External Input Clock Timing Oscillation settling time XCIN VCC tSUBOSC Figure 5.6 XCIN Sub-Clock Oscillation Settling Time R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 96 of 1931 RX62N RX621 5. Electrical Characteristics 5.3.2 Table 5.9 Control Signal Timing Control Signal Timing Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V Ta = -40 to +85C Item RES# pulse width (except for programming or erasure of the ROM or data-flash memory or blank checking of the data-flash memory*1) Internal reset time*3 NMI pulse width IRQ pulse width Symbol tRESW *2 Min. 20 1.5 Max. -- -- -- -- -- Unit tIcyc s s ns ns Test Conditions Figure 5.7 tRESW2 tNMIW tIRQW 35 200 200 Figure 5.8 Figure 5.9 Note 1. Do not allow a reset by the signal on the RES# pin during programming or erasure of the ROM or data-flash memory or during blank checking of the data-flash memory. For details, see section 37.13, Usage Notes, in section 37., ROM (Flash Memory for Code Storage). Note 2. Both the time and the number of cycles should satisfy the specifications. Note 3. This is to specify the FCU reset and the WDT reset. Note 4. tIcyc: ICLK cycles RES# tRESW Figure 5.7 Reset Input Timing NMI tNMIW Figure 5.8 NMI Interrupt Input Timing IRQ tIRQW Figure 5.9 IRQ Interrupt Input Timing R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 97 of 1931 RX62N RX621 5. Electrical Characteristics 5.3.3 Table 5.10 Bus Timing Bus Timing [176-pin LFBGA/145-pin TFLGA/144-pin LQFP] Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V ICLK = 8 to 100MHz, BCLK = 8 to 100MHz, SDCLK = 8 to 50MHz Ta = -40 to +85C Output load conditions: VOH = VCCx0.5, VOL = VCCx0.5, IOH = -1.0mA, IOL = 1.0mA, C = 30pF Item Address delay time Byte control delay time CS# delay time RD# delay time Read data setup time Read data hold time WR# delay time Write data delay time Write data hold time WAIT# setup time WAIT# hold time Address delay time 2 (SDRAM) CS# delay time 2 (SDRAM) DQM delay time (SDRAM) CKE delay time (SDRAM) Read data setup time 2 (SDRAM) Read data hold time 2 (SDRAM) Write data delay time 2 (SDRAM) Write data hold time 2 (SDRAM) WE# delay time (SDRAM) RAS# delay time (SDRAM) CAS# delay time (SDRAM) Symbol tAD tBCD tCSD tRSD tRDS tRDH tWRD tWDD tWDH tWTS tWTH tAD2 tCSD2 tDQMD tCKED tRDS2 tRDH2 tWDD2 tWDH2 tWED tRASD tCASD Min. -- -- -- -- 15 0.0 -- -- 0 15 0.0 1 1 1 1 12 0 -- 1 1 1 1 Max. 15 15 15 15 -- -- 15 15 -- -- -- 15 15 15 15 -- -- 15 -- 15 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 5.22 to Figure 5.28 Figure 5.14 Test Conditions Figure 5.10 to Figure 5.13 R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 98 of 1931 RX62N RX621 5. Electrical Characteristics Table 5.11 Bus Timing [100-pin LQFP/85-pin TFLGA] Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V ICLK = 8 to 100MHz, PCLK = 8 to 50MHz, BCLK = 8 to 50MHz Ta = -40 to +85C Output load conditions: VOH = VCC x 0.5, VOL = VCC x 0.5, IOH = -1.0mA, IOL = 1.0mA, C = 30pF Item Address delay time Byte control delay time CS# delay time RD# delay time Read data setup time Read data hold time WR# delay time Write data delay time Write data hold time WAIT# setup time WAIT# hold time Symbol tAD tBCD tCSD tRSD tRDS tRDH tWRD tWDD tWDH tWTS tWTH Min. -- -- -- -- 15 0.0 -- -- 0 15 0.0 Max. 30 30 30 30 -- -- 30 35 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns Figure 5.14 Test Conditions Figure 5.10 to Figure 5.13 R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 99 of 1931 RX62N RX621 5. Electrical Characteristics CSRWAIT:2 RDON:1 CSON:0 TW1 BCLK Byte write strobe mode tAD A23 to A0 tAD TW2 Tend CSROFF:1 Tn1 Th 1-write strobe mode A23 to A1 tAD tAD tBCD BC3# to BC0# tBCD Common to both byte write strobe mode and 1-write strobe mode CS7# to CS0# tCSD tCSD tRSD RD# (Read) tRSD tRDS D31 to D0 (Read) tRDH Figure 5.10 External Bus Timing/Normal Read Cycle (Bus Clock Synchronized) R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 100 of 1931 RX62N RX621 5. Electrical Characteristics CSWWAIT:2 WRON:1 WDON:1*1 CSON:0 TW1 BCLK Byte write strobe mode tAD A23 to A0 tAD TW2 Tend CSWOFF:1 WDOFF:1*1 Tn1 Th 1-write strobe mode A23 to A1 tAD tAD tBCD BC3# to BC0# tBCD Common to both byte write strobe mode and 1-write strobe mode CS7# to CS0# tCSD tCSD tWRD tWRD WR3# to WR0#, WR# (Write) tWDD D31 to D0 (Write) tWDH Note1: Be sure to specify WDON and WDOFF as at least one cycle of BCLK. Figure 5.11 External Bus Timing/Normal Write Cycle (Bus Clock Synchronized) R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 101 of 1931 RX62N RX621 5. Electrical Characteristics CSRWAIT:2 RDON:1 CSON:0 TW1 TW2 Tend CSPRWAIT:2 RDON:1 Tpw1 Tpw2 Tend CSPRWAIT:2 RDON:1 Tpw1 Tpw2 Tend CSPRWAIT:2 RDON:1 Tpw1 Tpw2 Tend CSROFF:1 Tn1 Th BCLK Byte write strobe mode A23 to A0 1-write strobe mode A23 to A1 tBCD tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD tBCD BC3# to BC0# Common to both byte write strobe mode and 1-write strobe mode tCSD tRSD tRSD tRSD tRSD tRSD tRSD tRSD tRSD tCSD CS7# to CS0# RD# (Read) tRDS D31 to D0 (Read) tRDH tRDS tRDH tRDS tRDH tRDS tRDH Figure 5.12 External Bus Timing/Page Read Cycle (Bus Clock Synchronized) CSWWAIT:2 WRON:1 WDON:1*1 CSON:0 TW1 BCLK Byte write strobe mode A23 to A0 1-write strobe mode A23 to A1 tAD tAD TW2 Tend WDOFF:1*1 Tdw1 CSPWWAIT:2 WRON:1 WDON:1*1 Tpw1 WDOFF:1*1 Tpw2 Tend Tdw1 CSPWWAIT:2 WRON:1 WDON:1*1 Tpw1 CSWOFF:1 WDOFF:1*1 Tpw2 Tend Tn1 Th tAD tAD tAD tAD tAD tAD tBCD BC3# to BC0# tBCD Common to both byte write strobe mode and 1-write strobe mode CS7# to CS0# tCSD tCSD tWRD tWRD tWRD tWRD tWRD tWRD WR3# to WR0#, WR# (Write) tWDD D31 to D0 (Write) tWDD tWDD tWDH tWDH tWDH Note1: Be sure to specify WDON and WDOFF as at least one cycle of BCLK. Figure 5.13 External Bus Timing/Page Write Cycle (Bus Clock Synchronized) R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 102 of 1931 RX62N RX621 5. Electrical Characteristics CSRWAIT:3 CSWWAIT:3 TW1 BCLK TW2 TW3 (Tend) Tend Tn1 Th A23 to A0 CS7# to CS0# RD# (Read) WR# (Write) External wait tWTS tWTH WAIT# tWTS tWTH Figure 5.14 External Bus Timing/External Wait Control R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 103 of 1931 RX62N RX621 5. Electrical Characteristics SDRAM command SDCLK tAD2 A18 to A0 tAD2 AP* ACT RD PRA tAD2 Row Address Column Address tAD2 tAD2 tAD2 tAD2 tAD2 PRA Command tCSD2 SDCS# tRASD RAS# tCSD2 tCSD2 tCSD2 tCSD2 tCSD2 tRASD tRASD tRASD tCASD CAS# tCASD tWED WE# (High) tDQMD DQMn tRDS2 D31 to D0 tRDH2 tWED CKE Note 1: Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 5.15 SDRAM Space Single Read Bus Timing R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 104 of 1931 RX62N RX621 5. Electrical Characteristics SDRAM command SDCLK ACT WR PRA tAD2 A18 to A0 tAD2 AP*1 tCSD2 SDCS# tRASD RAS# Row Address tAD2 Column Address tAD2 tAD2 tAD2 tAD2 tAD2 PRA command tCSD2 tCSD2 tCSD2 tCSD2 tCSD2 tRASD tRASD tRASD tCASD CAS# tWED WE# (High) tDQMD DQMn tWDD2 D31 to D0 tCASD tWED tWED tWED CKE tWDH2 Note 1: Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 5.16 SDRAM Space Single Write Bus Timing R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 105 of 1931 RX62N RX621 5. Electrical Characteristics ACT SDCLK tAD2 tAD2 RD RD RD RD PRA tAD2 tAD2 C1 C2 tAD2 tAD2 tAD2 C3 tAD2 A18 to A0 C0 Row Address (Column Address) tAD2 tAD2 tAD2 tAD2 PRA command tAD2 AP*1 tCSD2 tCSD2 tCSD2 tCSD2 tCSD2 SDCS# tRAS D tRAS D tRAS tRAS D D tRAS D RAS# tCAS D tCAS D tCAS D CAS# tWED tWED WE# High CKE tDQMD tDQMD DQMn tRDS2 tRDH2 tRDS2 tRDH2 D31 to D0 Note 1: Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 5.17 SDRAM Space Multiple Read Bus Timing R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 106 of 1931 RX62N RX621 5. Electrical Characteristics ACT WR WR WR WR PRA SDCLK tAD2 tAD2 tAD2 tAD2 C1 C2 tAD2 C3 tAD2 tAD2 tAD2 A18 to A0 C0 Row Address (Column Address) tAD2 tAD2 tAD2 tAD2 tAD2 AP*1 tCSD2 tCSD2 tCSD2 PRA command tCSD2 tCSD2 SDCS# tRAS tRAS D D tRAS tRAS tRAS D D D RAS# tCAS D tCAS D tCAS D CAS# tWED tWED WE# High CKE tDQMD tDQMD DQMn tWDD2 tWDH2 tWDD2 tWDH2 D31 to D0 Note 1: Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 5.18 SDRAM Space Multiple Write Bus Timing R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 107 of 1931 RX62N RX621 5. Electrical Characteristics SDRAM command SDCLK ACT RD RD RD RD PRA ACT RD RD RD RD PRA t AD2 t AD2 C0 (Column Address 0) t AD2 C1 t AD2 t AD2 C2 C3 t AD2 t AD2 t AD2 R1 t AD2 C4 t AD2 t AD2 t AD2 C5 t AD2 C6 t AD2 C7 t AD2 t AD2 A18 to A0 Row Address t AD2 t AD2 t AD2 t AD2 t AD2 t AD2 AP*1 t CSD2 t CSD2 t CSD2 PRA command PRA command t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 SDCS# t RASD t RASD t RASD t RASD t RASD t RASD t RASD t RASD RAS# t CASD t CASD t CASD t CASD CAS# t WED t WED t WED t WED WE# (High) CKE tDQMD DQMn t RDS2 t RDH2 t RDS2 t RDH2 t RDS2 t RDH2 t RDS2 t RDH2 D31 to D0 Note 1: Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 5.19 SDRAM Space Multiple Read Line Stride Bus Timing R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 108 of 1931 RX62N RX621 5. Electrical Characteristics SDRAM command SDCLK t AD2 MRS t AD2 A18 to A0 t AD2 t AD2 AP*1 t CSD2 t CSD2 SDCS# t RASD t RASD RAS# t CASD t CASD CAS# t WED t WED WE# (High) CKE DQMn (Hi-Z) D31 to D0 Note 1: Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 5.20 SDRAM Space Mode Register Set Bus Timing R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 109 of 1931 RX62N RX621 5. Electrical Characteristics SDRAM command SDCLK Ts (RFA) (RFS) (RFX) (RFA) t AD2 t AD2 A18 to A0 t AD2 t AD2 AP*1 t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 t CSD2 SDCS# t RASD t RASD t RASD t RASD t RASD t RASD t RASD RAS# t CASD t CASD t CASD t CASD t CASD t CASD t CASD CAS# (High) WE# t CKED t CKED CKE t DQMD t DQMD DQMn D31 to D0 (Hi-Z) Note 1: Address pins for output of the precharge-setting command (Precharge-sel) for SDRAM. Figure 5.21 SDRAM Space Self-Refresh Bus Timing R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 110 of 1931 RX62N RX621 5. Electrical Characteristics 5.3.4 Table 5.12 EXDMAC Timing EXDMAC Timing Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V ICLK = 8 to 100MHz, PCLK = 8 to 50MHz, BCLK = 8 to 100MHz, SDCLK = 8 to 50MHz Ta = -40 to +85C Item EXDMAC EDREQ setup time EDREQ hold time EDACK delay time Symbol tEDRQS tEDRQH tEDACD Min. 20 5 -- Max. -- -- 15 Unit ns ns ns Figure 5.23 and Figure 5.24 Test Conditions Figure 5.22 BCLK tEDRQS tEDRQH EDREQ0 EDREQ1 Figure 5.22 EDREQ0 and EDREQ1 Input Timing BCLK tEDACD EDACK0 EDACK1 tEDACD Figure 5.23 EDACK0 and EDACK1 Single-Address Transfer Timing (for a CS Area) BCLK tEDACD EDACK0 EDACK1 tEDACD Figure 5.24 EDACK0 and EDACK1 Single-Address Transfer Timing (for SDRAM) R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 111 of 1931 RX62N RX621 5. Electrical Characteristics 5.3.5 Table 5.13 Timing of On-Chip Peripheral Modules Timing of On-Chip Peripheral Modules (1) Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V PCLK = 8 to 50MHz Ta = -40 to +85C Item I/O ports Output data delay time Input data setup time Input data hold time MTU2 Output compare output delay time Input capture input setup time Input capture input pulse width (single-edge setting) Input capture input pulse width (both-edge setting) Timer input setup time Timer clock pulse width (single-edge setting) Timer clock pulse width (both-edge setting) Timer clock pulse width (phase coefficient mode) POE2 POE# input setup time POE# input pulse width PPG 8-bit timer Pulse output delay time Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width WDT Single-edge setting Both-edge setting Symbol tPWD tPRS tPRH tTOCD tTICS tTICW tTICW tTCKS tTCKWH/L tTCKWH/L tTCKWH/L tPOES tPOEW tPOD tTMOD tTMRS tTMCS tTMCWH tTMCWL tWOVD Min. -- 25 25 -- 20 1.5 x tPcyc 2.5 x tPcyc 20 1.5 x tPcyc 2.5 x tPcyc 2.5 x tPcyc 50 1.5 x tPcyc -- -- 25 25 1.5 x tPcyc 2.5 x tPcyc -- Max. 40 -- -- 40 -- -- -- -- -- -- -- -- -- 40 40 -- -- -- -- 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 5.33 Figure 5.29 Figure 5.30 Figure 5.31 Figure 5.32 Figure 5.26 Test Conditions Figure 5.25 Figure 5.27 Figure 5.28 Overflow output delay time R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 112 of 1931 RX62N RX621 5. Electrical Characteristics Table 5.13 Timing of On-Chip Peripheral Modules (1) (1/2) Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V PCLK = 8 to 50MHz Ta = -40 to +85C Item SCI Input clock cycle Asynchronous Clock synchronous Input clock pulse width Input clock rise time Input clock fall time Output clock cycle Asynchronous Clock synchronous Output clock pulse width Output clock rise time Output clock fall time Transmit data delay time (clock synchronous) Receive data setup time (clock synchronous) Receive data hold time (clock synchronous) A/D converter 10-bit A/D converter trigger input setup time 12-bit A/D converter trigger input setup time tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS tTRGS tSCKW tSCKr tSCKf tScyc Symbol tScyc Min. 4 x tPcyc 6 x tPcyc 0.4 x tScyc -- -- 4 x tPcyc 6 x tPcyc 0.4 x tScyc -- -- -- 40 40 25 25 Max. -- -- 0.6 x tScyc 20 20 -- -- 0.6 x tScyc 20 20 40 -- -- -- -- ns ns ns ns ns ns ns ns Figure 5.36 ns ns ns ns Unit ns Test Conditions Figure 5.34 and Figure 5.35 R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 113 of 1931 RX62N RX621 5. Electrical Characteristics Table 5.14 Timing of On-Chip Peripheral Modules (2) (1/2) Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V PCLK = 8 to 50MHz Ta = -40 to +85C Item CAN Transmit data delay time Receive data setup time Receive data hold time RSPI RSPCK clock cycle Master Slave RSPCK clock high pulse width Master Slave RSPCK clock low pulse width Master Slave RSPCK clock rise/fall time Output [176-pin LFBGA/ 145-pin TFLGA/ 144-pin LQFP] Output [100-pin LQFP/ 85-pin TFLGA] Input Note 1. tPcyc: PCLK cycle tSPCKr, tSPCKf tSPCKWL tSPCKWH Symbol tCTXD tCRXS tCRXH tSPcyc Min. -- 40.0 40.0 2 8 (tSPcyc-tSPCKR-tSPCKF) / 2-3 (tSPcyc-tSPCKR-tSPCKF) / 2 (tSPcyc-tSPCKR-tSPCKF) / 2-3 (tSPcyc-tSPCKR-tSPCKF) / 2 -- Max. 40.0 -- -- 4096 4096 -- -- -- -- 5 ns ns ns Unit ns ns ns tPcyc *1 Figure 5.38 Test Conditions Figure 5.37 -- 10 -- 1 s R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 114 of 1931 RX62N RX621 5. Electrical Characteristics Table 5.14 Timing of On-Chip Peripheral Modules (2) (2/2) Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V PCLK = 8 to 50MHz Ta = -40 to +85C Item RSPI Data input setup time Master [176-pin LFBGA/ 145-pin TFLGA/ 144-pin LQFP] Master [100-pin LQFP/ 85-pin TFLGA] Slave Data input hold time Master Slave SSL setup time Master Slave SSL hold time Master Slave Data output delay time Master [176-pin LFBGA/ 145-pin TFLGA/ 144-pin LQFP] Master [100-pin LQFP/ 85-pin TFLGA] Slave [176-pin LFBGA/ 145-pin TFLGA/ 144-pin LQFP] Slave [100-pin LQFP/ 85-pin TFLGA] Note 1. tPcyc: PCLK cycle tOD tLAG tLEAD tH Symbol tSU Min. 16 Max. -- Unit ns Test Conditions Figure 5.39 to Figure 5.42 30 -- 20-2 x tPcyc 0 20+2 x tPcyc 1 4 1 4 -- -- -- -- 8 -- 8 -- 20 tSPcyc tPcyc tSPcyc tPcyc ns ns -- 30 -- 3 x tPcyc+40 -- 3 x tPcyc+50 R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 115 of 1931 RX62N RX621 5. Electrical Characteristics Table 5.15 Timing of On-Chip Peripheral Modules (3) Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V PCLK = 8 to 50MHz Ta = -40 to +85C Item RSPI Data output hold time Master Slave Sucessive transmission delay time Master Slave MOSI, MISO rise/fall time Output [176-pin LFBGA/ 145-pin TFLGA/ 144-pin LQFP] Output [100-pin LQFP/ 85-pin TFLGA] Input SSL rise/fall time Output [176-pin LFBGA 145-pin TFLGA 144-pin LQFP] Output [100-pin LQFP/ 85-pin TFLGA] Input Slave access time Slave output release tim Note 1. tPcyc: PCLK cycle tSA tREL tSSLr, tSSLf tDr, tDf tTD Symbol tOH Min. 0 0 tSPcyc+2 x tPcyc 4 x tPcyc -- Max. -- -- 8 x tSPcyc +2 x tPcyc -- 5 ns ns Unit ns Test Conditions Figure 5.39 to Figure 5.42 -- 10 -- -- 1 5 s ns -- 10 -- -- -- 1 4 3 s tPcyc tPcyc Figure 5.41 and Figure 5.42 R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 116 of 1931 RX62N RX621 5. Electrical Characteristics Table 5.16 Timing of On-Chip Peripheral Modules (4) (1/2) Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V PCLK = 8 to 50MHz Ta = -40 to +85C Ta = -40 to +85C Item RIIC (Standard-mode, SMBus) ICFER.FMPE = 0 SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rising time SCL, SDA input falling time SCL, SDA input spike pulse removal time SDA input bus free time Start condition input hold time Re-start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load RIIC (Fast-mode) SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rising time SCL, SDA input falling time SCL, SDA input spike pulse removal time SDA input bus free time Start condition input hold time Re-start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load Symbol tSCL tSCLH tSCLL tSr tSf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb tSCL tSCLH tSCLL tSr tSf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb Min.*1*2 6(12) x tIICcyc + 1300 3(6) x tIICcyc + 300 3(6) x tIICcyc + 300 -- -- 0 3(6) x tIICcyc + 300 tIICcyc + 300 1000 1000 tIICcyc + 50 0 -- 6(12) x tIICcy + 600 3(6) x tIICcy + 300 3(6) x tIICcy + 300 20+0.1Cb 20+0.1Cb 0 3(6) x tIICcy + 300 tIICcy + 300 300 300 tIICcy + 50 0 -- Max. -- -- -- 1000 300 1(4) x tIICcy -- -- -- -- -- -- 400 -- -- -- 300 300 1(4) x tIICcy -- -- -- -- -- -- 400 Unit ns ns ns ns ns ns ns ns ns ns ns ns pF ns ns ns ns ns ns ns ns ns ns ns ns pF Test Conditions Figure 5.43 Note: tIICcyc: RIIC internal reference clock (IIC) cycles Note 1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1. Note 2. Cb indicates the total capacity of the bus line. R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 117 of 1931 RX62N RX621 5. Electrical Characteristics Table 5.16 Timing of On-Chip Peripheral Modules (4) (2/2) Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V PCLK = 8 to 50MHz Ta = -40 to +85Cz Ta = -40 to +85C Item RIIC (Fast-mode+) ICFER.FMPE = 1 SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rising time SCL, SDA input falling time SCL, SDA input spike pulse removal time SDA input bus free time Start condition input hold time Re-start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load Symbol tSCL tSCLH tSCLL tSr tSf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb Min.*1*2 6(12) x tIICcyc + 240 3(6) x tIICcyc + 120 3(6) x tIICcyc + 120 -- -- 0 3(6) x tIICcyc + 120 tIICcyc + 120 120 120 tIICcyc + 20 0 -- -- -- -- -- 550 Max. -- -- -- 120 120 1(4) x tIICcyc -- Unit ns ns ns ns ns ns ns ns ns ns ns ns pF Test Conditions Figure 5.43 Note: tIICcyc: RIIC internal reference clock (IIC) cycles Note 1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1. Note 2. Cb indicates the total capacity of the bus line. R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 118 of 1931 RX62N RX621 5. Electrical Characteristics Table 5.17 Timing of On-Chip Peripheral Modules (5) (1/2) Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V PCLK = 8 to 50MHz Ta = -40 to +85C Item ETHERC(RMII) REF50CK cycle time REF50CK frequency Typ. 50MHz REF50CK duty REF50CK rise/fall time RMII_xxxx*1 output delay time RMII_xxxx*2 setup time RMII_xxxx*2 hold time RMII_xxxx*1*2 rise/fall time ET_MDIO setup time ET_MDIO hold time ET_MDIO output hold time*3 ET_WOL output delay time -- Tckr/ckf Tco Tsu Thd Tr/Tf tMDIOs tMDIOh tMDIODh tWOLd 35 0.5 2.5 3 1 0.5 10 10 5 1 65 3.5 12.5 -- -- 6 -- -- -- 20 % ns ns ns ns ns ns ns ns ns Figure 5.49 Figure 5.50 Figure 5.48 Symbol Tck -- Min. 20 -- Max. -- 50 + 100ppm Unit ns MHz Test Conditions Figure 5.44 to Figure 5.47 Note 1. RMII_TXD_EN, RMII_TXD1, RMII_TXD0 Note 2. RMII_CRS_DV, RMII_RXD1, RMII_RXD0, RMII_RX_ER Note 3. The user program must make settings so that this stipulation is satisfied. R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 119 of 1931 RX62N RX621 5. Electrical Characteristics Table 5.17 Timing of On-Chip Peripheral Modules (5) (2/2) Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V PCLK = 8 to 50MHz Ta = -40 to +85C Item ETHERC(MII) ET_TX_CLK cycle time ET_TX_EN output delay time ET_ETXD0 to ET_ETXD3 output delay time ET_CRS setup time ET_CRS hold time ET_COL setup time ET_COL hold time ET_RX_CLK cycle time ET_RX_DV setup time ET_RX_DV hold time ET_ERXD0 to ET_ERXD3 setup time ET_ERXD0 to ET_ERXD3 hold time ET_RX_ER setup time ET_RX_ER hold time ET_MDIO setup time ET_MDIO hold time ET_MDIO utput hold time ET_WOL output delay time Symbol tTcyc tTENd tMTDd tCRSs tCRSh tCOLs tCOLh tTRcyc tRDVs tRDVh tMRDs tMRDh tRERs tRESh tMDIOs tMDIOh tMDIOdh tWOLd Min. 40 1 1 10 10 10 10 40 10 10 10 10 10 10 10 10 5 1 -- -- -- -- -- -- -- -- 20 Max. -- 20 20 -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 5.56 Figure 5.57 Figure 5.55 Figure 5.54 -- Figure 5.53 Figure 5.52 Test Conditions -- Figure 5.51 Note 1. RMII_TXD_EN, RMII_TXD1, RMII_TXD0 Note 2. RMII_CRS_DV, RMII_RXD1, RMII_RXD0, RMII_RX_ER Note 3. The user program must make settings so that this stipulation is satisfied. R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 120 of 1931 RX62N RX621 5. Electrical Characteristics Table 5.18 Timing of On-Chip Peripheral Modules (6) Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V PCLK = 8 to 50MHz Ta = -40 to +85C Item TCK clock cycle time TCK clock high pulse width TCK clock low pulse width TCK clock rising time TCK clock falling time TRST# pulse width TMS setup time TMS hold time TDI setup time TDI hold time TDO data delay time Symbol tTCKcyc tTCKH tTCKL tTCKr tTCKf tTRSTW tTMSS tTMSH tTDIS tTDIH tTDOD Min. 100 45 45 -- -- 20 20 20 20 20 -- Typ. -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- 5 5 -- -- -- -- -- 40 Unit ns ns ns ns ns tTCKcyc ns ns ns ns ns Figure 5.59 Figure 5.60 Test Conditions Figure 5.58 T1 T2 PCLK tPRS Input port (read) tPRH tPWD Output port (write) Figure 5.25 I/O Port Input/Output Timing PCLK tTOCD Output compare output Input capture input tTICS tTICW Figure 5.26 MTU2 Input/Output Timing R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 121 of 1931 RX62N RX621 5. Electrical Characteristics PCLK tTCKS MTCLKA to MTCLKH tTCKWL tTCKWH tTCKS Figure 5.27 MTU2 Clock Input Timing PCLK tPOES POEn# input tPOEW Figure 5.28 POE# Input Timing PCLK tPOD PO31 to PO0 Figure 5.29 PPG Output Timing PCLK tTMOD TMO0 to TMO3 Figure 5.30 8-Bit Timer Output Timing R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 122 of 1931 RX62N RX621 5. Electrical Characteristics PCLK tTMRS TMRI0 to TMRI3 Figure 5.31 8-Bit Timer Reset Input Timing PCLK tTMCS TMCI0 to TMCI3 tTMCWL tTMCWH tTMCS Figure 5.32 8-Bit Timer Clock Input Timing PCLK tWOVD WDTOVF# tWOVD Figure 5.33 WDT Output Timing tSCKW SCKn n = 0 to 3, 5, 6 tSCKr tSCKf tScyc Figure 5.34 SCK Clock Input Timing R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 123 of 1931 RX62N RX621 5. Electrical Characteristics SCKn tTXD TxDn tRXS tRXH RxDn n = 0 to 3, 5, 6 Figure 5.35 SCI Input/Output Timing: Clock Synchronous Mode PCLK tTRGS ADTRG0#-A/B ADTRG1# Figure 5.36 A/D Converter External Trigger Input Timing PCLK tCRXS CRX0 tCTXD CTX0 tCRXH Figure 5.37 CAN Input/Output Timing R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 124 of 1931 RX62N RX621 5. Electrical Characteristics tSPCKWH RSPCKA to RSPCKB Master select output tSPCKr VOH VOL VOL tSPCKWL VOH VOH tSPCKf VOH VOL tSPcyc tSPCKf VIH VIH VIL tSPcyc tSPCKWH RSPCKA to RSPCKB Slave select output tSPCKr VIH VIL VIL tSPCKWL VIH Figure 5.38 RSPI Clock Timing tTD SSLA3 to SSLA0 SSLB3 to SSLB0 output RSPCKA to RSPCKB CPOL=0 output RSPCKA to RSPCKB CPOL=1 output MISOA to MISOB input tLEAD tLAG tSSLrtSSLf tSU tH DATA tOH MSB OUT DATA tOD LSB OUT IDLE MSB OUT LSB IN MSB IN MSB IN tDrtDf MOSIA to MOSIB output Figure 5.39 RSPI Timing (Master, CPHA = 0) R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 125 of 1931 RX62N RX621 5. Electrical Characteristics tTD SSLA3 to SSLA0 SSLB3 to SSLB0 output RSPCKA to RSPCKB CPOL=0 output RSPCKA to RSPCKB CPOL=1 output MISOA to MISOB input tOH MOSIA to MOSIB output MSB OUT tLEAD tLAG tSSLrtSSLf tSU tH DATA tOD DATA LSB OUT LSB IN tDrtDf IDLE MSB OUT MSB IN MSB IN Figure 5.40 RSPI Timing (Master, CPHA = 1) tTD SSLA0 SSLB0 input RSPCKA to RSPCKB CPOL=0 input RSPCKA to RSPCKB CPOL=1 input MISOA to MISOB output tSU MOSIA to MOSIB input tLEAD tLAG tSA tOH MSB OUT tH DATA DATA tOD LSB OUT tDrtDf LSB IN tREL MSB IN MSB OUT MSB IN MSB IN Figure 5.41 RSPI Timing (Slave, CPHA = 0) R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 126 of 1931 RX62N RX621 5. Electrical Characteristics tTD SSLA0 SSLB0 input RSPCKA to RSPCKB CPOL=0 input RSPCKA to RSPCKB CPOL=1 input MISOA to MISOB output tLEAD tLAG tSA tOH LSB OUT (Last data) MSB OUT tSU tH tOD DATA tDrtDf DATA LSB IN LSB OUT tREL MSB OUT MOSIA to MOSIB input MSB IN MSB IN Figure 5.42 RSPI Timing (Slave, CPHA = 1) SDA0, SDA1 VIH VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL0, SCL1 P *1 S *1 tSf tSCLL tSCL tSr tSDAH Test conditions VIH = VCCx0.7, VIL = VCCx0.3 VOL = 0.6V, IOL = 6mA(ICFER.FMPE = 0) VOL = 0.4V, IOL = 15mA(ICFER.FMPE = 1) Sr *1 tSDAS P1 Note1: S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Restart condition Figure 5.43 I2C Bus Interface Input/Output Timing R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 127 of 1931 RX62N RX621 5. Electrical Characteristics Tck 90% Tckr Tckf REF50CK 50% 10% Tr 90% Tco Tf Tsu Thd RMII_xxxx *1 50% Signal 10% transitions Signal Signal transitions Signal Signal transitions Note1. RMII_TXD_ENRMII_TXD1RMII_TXD0RMII_CRS_DVRMII_RXD1RMII_RXD0RMII_RX_ER Figure 5.44 REF50CK and RMII Signal Timing Tck REF50CK Tco RMII_TXD_EN RMII_TXD1 RMII_TXD0 Tco Preamble SFD DATA CRC Figure 5.45 RMII Transmission Timing REF50CK Tsu RMII_CRS_DV Tsu RMII_RXD1 RMII_RXD0 RMII_RX_ER L Preamble SFD DATA CRC Thd Thd Figure 5.46 RMII Reception Timing (Normal Operation) R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 128 of 1931 RX62N RX621 5. Electrical Characteristics REF50CK RMII_CRS_DV RMII_RXD1 RMII_RXD0 RMII_RX_ER Preamble SFD DATA Tsu Thd xxxx Figure 5.47 RMII Reception Timing (Error Occurrence) ET_MDC tMDIOs ET_MDIO tMDIOh Figure 5.48 MDIO Input Timing (RMII) ET_MDC tMDIOdh ET_MDIO Figure 5.49 MDIO Output Timing (RMII) REF50CK tWOLd ET_WOL Figure 5.50 WOL Output Timing (RMII) R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 129 of 1931 RX62N RX621 5. Electrical Characteristics ET_TX_CLK tTENd ET_TX_EN tMTDd ET_ETXD[3:0] Preamble SFD DATA CRC ET_TX_ER tCRSs ET_CRS tCRSh ET_COL Figure 5.51 MII Transmission Timing (Normal Operation) ET_TX_CLK ET_TX_EN ET_ETXD[3:0] Preamble JAM ET_TX_ER ET_CRS tCOLs ET_COL tCOLh Figure 5.52 MII Transmission Timing (Conflict Occurrence) ET_RX_CLK tRDVs ET_RX_DV tMRDs ET_ERXD[3:0] Preamble SFD tMRDh DATA CRC tRDVn ET_RX_ER Figure 5.53 MII Reception Timing (Normal Operation) R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 130 of 1931 RX62N RX621 5. Electrical Characteristics ET_RX_CLK ET_RX_DV ET_ERXD[3:0] Preamble SFD DATA tRERs tRERh XXXX ET_RX_ER Figure 5.54 MII Reception Timing (Error Occurrence) ET_MDC tMDIOs ET_MDIO tMDIOh Figure 5.55 MDIO Input Timing (MII) ET_MDC tMDIOdh ET_MDIO Figure 5.56 MDIO Output Timing(MII) ET_RX_CLK tWOLd ET_WOL Figure 5.57 WOL Output Timing(MII) R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 131 of 1931 RX62N RX621 5. Electrical Characteristics tTCKcyc tTCKH TCK tTCKf tTCKL tTCKr Figure 5.58 Boundary Scan TCK Timing TCK RES# TRST# tTRSTW Figure 5.59 Boundary Scan TRST# Timing TCK tTMSS TMS tTMSH tTDIS TDI tTDOD tTDIH TDO Figure 5.60 Boundary Scan Input/Output Timing R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 132 of 1931 RX62N RX621 5. Electrical Characteristics 5.4 USB Characteristics Internal USB Full-Speed Characteristics (DP, DM Pin Characteristics) Table 5.19 Conditions: VCC = PLLVCC = AVCC = VCC_USB = 3.0 to 3.6V, VREFH = 3.0V to AVCC VSS = PLLVSS = AVSS = VREFL = VCC_USB = 0V PCLK = 24 to 50MHz Ta = -40 to +85C Item Input characteristics Input high level voltage Input low level voltage Differential input Sensitivity Differential commom mode range Output characteristics Output high level voltage Output low level voltage Cross over voltage Rising time Falling time Rising/falling time ratio Output resistance Symbol VIH VIL VDI VCM VOH VOL VCRS tLr tLf tLr / tLf ZDRV Min. 2.0 -- 0.2 0.8 2.8 0.0 1.3 4 4 90 28 Max. -- 0.8 -- 2.5 3.6 0.3 2.0 20 20 111.11 44 Unit V V V V V V V ns ns % tLr / tLf Rs = 22 included IOH = -200A IOL = 2mA DP -- DM Test Conditions Figure 5.61 and Figure 5.62 DPDM VCRS 90 10 90 10 tLr tLf Figure 5.61 DP, DM Output Timing (Full-Speed) dp Observation point 22 50pF dm 22 50pF Figure 5.62 Test Circuit (Full-Speed) R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 133 of 1931 RX62N RX621 5. Electrical Characteristics 5.5 A/D Conversion Characteristics 10-Bit A/D Conversion Characteristics Table 5.20 Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V PCLK = 8 to 50MHz Ta = -40 to +85C Item Resolution Conversion time*1 (PCLK = 50-MHz operation) With 0.1-F external capacitor Without external capacitor Permissible signal source impedance (max.) = 1.0 k Permissible signal source impedance (max.) = 5.0 k Analog input capacitance INL integral nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy DNL differential nonlinearity error -- -- -- -- -- -- -- -- 1.5 1.5 1.5 0.5 1.5 0.5 6.0 3.0 3.0 3.0 -- 3.0 1.0 pF LSB LSB LSB LSB LSB LSB 2.6 (2.1)*3 -- -- 1.0 (0.5)*3 -- -- Sampling 25 states Sampling 105 states When the capacitor is charged enough*2 Min. 10 0.8 (0.3)*3 Typ. 10 -- Max. 10 -- Unit bits s Sampling 15 states Test Conditions Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states is indicated. Note 2. The scanning is not supported. Note 3. The value in parentheses indicates the sampling time. Table 5.21 12-Bit A/D Conversion Characteristics Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V PCLK = 8 to 50MHz Ta = -40 to +85C Item Resolution Conversion time*1 Min. 12 1.0 2.0 Analog input capacitance Offset error Full-scale error Quantization error Absolute accuracy Nonlinearity error -- -- -- -- -- -- Typ. 12 -- -- -- 2.0 2.0 0.5 2.5 2.0 Max. 12 -- -- 30 7.5 7.5 -- 8.0 4.0 Unit bits s s pF LSB LSB LSB LSB LSB AVCC 3.0 AVCC 2.7 Test Conditions Note 1. The time conversion takes is the sum of the sampling interval and the time comparison takes (permissible signal-source impedance is up to 1.0 k) R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 134 of 1931 RX62N RX621 5. Electrical Characteristics 5.6 D/A Conversion Characteristics D/A Conversion Characteristics Table 5.22 Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V Ta = -40 to +85C Item Resolution Conversion time Absolute accuracy Min. 10 -- -- -- -- RO output resistance -- Typ. 10 -- 2.0 -- -- 3.6 Max. 10 3.0 4.0 3.0 2.0 -- Unit bits s LSB LSB LSB k 20-pF capacitive load 2-M resistive load 4-M resistive load 10-M resistive load Test Conditions 5.7 Power-on Reset Circuit, Voltage Detection Circuit Characteristics Power-on Reset Circuit, Voltage Detection Circuit Characteristics Table 5.23 Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V Ta = -40 to +85C Item Voltage detection level Power-on reset (POR) Voltage detection circuit (LVD) Symbol VPOR Vdet1 Vdet2 Internal reset time Min. VCC down time*1 Reply delay time tPOR tVOFF tdet Min. 2.48 2.75 3.05 20 200 -- Typ. 2.58 2.85 3.15 35 -- -- Max. 2.68 2.95 3.25 50 -- 200 ms s s Figure 5.64 and Figure 5.65 Unit V Test Conditions Figure 5.63 Figure 5.64 and Figure 5.65 Note 1. The power-off time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet1, and Vdet2 for the POR/ LVD. t VOFF VCC VPOR Internal reset signal (low valid) tPOR tdet tPOR Figure 5.63 Power-on Reset Timing R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 135 of 1931 RX62N RX621 5. Electrical Characteristics t VOFF VCC Vdet1 Internal reset signal (low valid) tdet tPOR Figure 5.64 Voltage Detection Circuit Timing (Vdet1) t VOFF Vdet2 VCC Internal reset signal (low valid) tdet tPOR Figure 5.65 Voltage Detection Circuit Timing (Vdet2) R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 136 of 1931 RX62N RX621 5. Electrical Characteristics 5.8 Oscillation Stop Detection Timing Oscillation Stop Detection Circuit Characteristics Table 5.24 Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V Ta = -40 to +85C Item Detection time Internal oscillation frequency when oscillation stop is detected Symbol tdr fMAIN Min. -- 0.5 Typ. -- -- Max. 1.0 7.0 Unit ms MHz Test Conditions Figure 5.66 Main clock oscillator tdr OSTDF* Nomal operation Abnomal operation Internal oscillation ICLK Note : * This indicates the OSTDF flag in the oscillation detection control register (OSTDCR). Figure 5.66 Oscillation Stop Detection Timing R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 137 of 1931 RX62N RX621 5. Electrical Characteristics 5.9 ROM (Flash Memory for Code Storage) Characteristics ROM (Flash Memory for Code Storage) Characteristics Table 5.25 Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V Temperature range for the programming/erasure operation: Ta = -40 to +85C Item Programming time 256 bytes 4 Kbytes 16 Kbytes 256 byte 4 Kbytes 16 Kbytes Erasure time 4 Kbytes 16 Kbytes 4 Kbytes 16 Kbytes Rewrite/erase cycle*1 Suspend delay time during writing First suspend delay time during erasing (in suspend priority mode) Second suspend delay time during erasing (in suspend priority mode) Suspend delay time during erasing (in erasure priority mode) Data hold time*3 tDRP 10 -- -- Year tSEED -- -- 1.7 ms tSESD2 -- -- 1.7 ms Symbol tP256 tP4K tP16K tP256 tP4K tP16K tE4K tE16K tE4K tE16K NPEC tSPD tSESD1 -- -- Min. -- -- -- -- -- -- -- -- -- -- Typ. 2 23 90 2.4 27.6 108 25 100 30 120 -- -- -- Max. 12 50 200 14.4 60 240 60 240 72 288 -- 120 120 Unit ms ms ms ms ms ms ms ms ms ms Times s s Figure 5.67 PCLK = 50-MHz operation PCLK = 50MHz NPEC 100 PCLK = 50MHz NPEC > 100 PCLK = 50MHz NPEC > 100 Test Conditions PCLK = 50MHz NPEC 100 Note 1. Definition of rewrite/erase cycle: The rewrite/erase cycle is the number of erasing for each block. When the rewrite/erase cycle is n times (n = 1000), erasing can be performed n times for each block. For instance, when 256-byte writing is performed 16 times for different addresses in 4Kbyte block and then the entire block is erased, the rewrite/erase cycle is counted as one. However, writing to the same address for several times as one erasing is not enabled (over writing is prohibited). Note 2. This indicates the minimum number that guarantees the characteristics after rewriting. (The guaranteed value is in the range from one to the minimum number.) Note 3. This indicates the characteristic when rewrite is performed within the specification range including the minimum number. R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 138 of 1931 RX62N RX621 5. Electrical Characteristics 5.10 Data Flash (Flash Memory for Data Storage) Characteristics Data Flash (Flash Memory for Data Storage) Characteristics Table 5.26 Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V Temperature range for the programming/erasure operation: Ta = -40 to +85C Item Programming time 8 bytes 128 bytes Erasure time 2 Kbytes Symbol tDP8 tDP128 tDE2K Min. -- -- -- Typ. 0.4 1 70 Max. 2 5 250 Unit ms ms ms Test Conditions PCLK = 50-MHz operation PCLK = 50-MHz operation Blank check time 8 bytes 2 Kbytes Rewrite/erase cycle*1 Suspend delay time during writing First suspend delay time during erasing (in suspend priority mode) Second suspend delay time during erasing (in suspend priority mode) Suspend delay time during erasing (in erasure priority mode) Data hold time*3 tDDRP 10 -- -- Year tDSEED -- -- 1.7 ms tDSESD2 -- -- 1.7 ms tDBC8 tDBC2K NDPEC tDSPD tDSESD1 -- -- 30000*2 -- -- -- -- -- -- -- 30 0.7 -- 120 120 s ms Times s s Figure 5.67 PCLK = 50-MHz operation PCLK = 50-MHz operationz Note 1. Definition of rewrite/erase cycle: The rewrite/erase cycle is the number of erasing for each block. When the rewrite/erase cycle is n times (n = 30000), erasing can be performed n times for each block. For instance, when 128-byte writing is performed 16 times for different addresses in 2Kbyte block and then the entire block is erased, the rewrite/erase cycle is counted as one. However, writing to the same address for several times as one erasing is not enabled (over writing is prohibited). Note 2. This indicates the minimum number that guarantees the characteristics after rewriting. (The guaranteed value is in the range from one to the minimum number.) Note 3. This indicates the characteristic when rewrite is performed within the specification range including the minimum number. R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 139 of 1931 RX62N RX621 5. Electrical Characteristics Write suspend FCU command Program Suspend tSPD FSTATR0.FRDY Ready Not Ready Ready Write pulse Programming Erasure suspend in suspend priority mode FCU command Erase Suspend tSESD1 FSTATR0.FRDY Ready Not Ready Ready Not Ready Resume Suspend tSESD2 Erasure pulse Erasing Erasing Erasure suspend in erasure priority mode FCU command Erase Suspend tSEED FSTATR0.FRDY Ready Not Ready Ready Erasure pulse Erasing Figure 5.67 Flash Memory Write/Erase Suspend Timing R01UH0033JJ0110 Rev.1.10 2010.12.24 Page 140 of 1931 RX62N Group, RX621 Group 5. Electrical Characteristics Write suspend FCU command Program Suspend tSPD FSTATR0.FRDY Ready Not Ready Ready Write pulse Programming Erasure suspend in suspend priority mode FCU command Erase Suspend tSESD1 FSTATR0.FRDY Ready Not Ready Ready Not Ready Resume Suspend tSESD2 Erasure pulse Erasing Erasing Erasure suspend in erasure priority mode FCU command Erase Suspend tSEED FSTATR0.FRDY Ready Not Ready Ready Erasure pulse Erasing Figure 5.67 Flash Memory Write/Erase Suspend Timing R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 141 of 146 RX62N Group, RX621 Group Appendix 1. Package Dimensions Appendix 1.Package Dimensions Information on the latest version of the package dimensions or mountings has been displayed in "Packages" on Renesas Electronics Corp. website. JEITA Package Code P-LFBGA176-13x13-0.80 RENESAS Code PLBG0176GA-A Previous Code BP-176/BP-176V MASS[Typ.] 0.45g wSA D wSB x4 v y1 S S A yS e A ZD e R P N M L K J H G F E D C B A A1 E Reference Symbol Dimension in Millimeters Min Nom 13.0 13.0 0.15 0.20 1.40 0.35 0.40 0.80 0.45 0.50 0.55 0.08 0.10 0.2 0.45 Max B D E v w A ZE A1 e b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 x y y1 SD SE ZD ZE 0.90 0.90 b xM S A B Figure A 176-Pin LFBGA (PLBG0176GA-A) Package Dimensions R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 142 of 146 RX62N Group, RX621 Group Appendix 1. Package Dimensions JEITA Package Code P-TFLGA145-9x9-0.65 RENESAS Code PTLG0145JB-A Previous Code - MASS[Typ.] 0.15g wSA D wSB x4 v y1 S S A yS e A ZD N M L K J H G F E D ZE Reference Symbol e E Dimension in Millimeters B Min Nom 9.0 9.0 Max D E v w A A1 e 1 2 3 4 5 6 7 b 8 9 10 11 12 13 xn S A B 0.15 0.20 1.2 C B A 0.65 0.30 0.35 0.40 0.08 0.1 0.20 b x y y1 SD SE ZD ZE 0.6 0.6 Figure B 145-Pin TFLGA (PTLG0145JB-A) Package Dimensions R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 143 of 146 RX62N Group, RX621 Group Appendix 1. Package Dimensions JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g HD *1 108 D 73 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1 109 72 c1 HE E c Reference Dimension in Millimeters Symbol *2 Terminal cross section 1 ZD A2 A 36 Index mark F ZE 144 37 L L1 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 *3 e y bp x Detail F Min Nom Max 19.9 20.0 20.1 19.9 20.0 20.1 1.4 21.8 22.0 22.2 21.8 22.0 22.2 1.7 0.05 0.1 0.15 0.17 0.22 0.27 0.20 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.10 1.25 1.25 0.35 0.5 0.65 1.0 Figure C 144-Pin LQFP (PLQP0144KA-A) Package Dimensions JEITA Package Code P-LQFP100-14x14-0.50 RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g HD *1 D 75 51 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 76 50 A1 bp b1 HE E c Reference Dimension in Millimeters Symbol *2 c1 c Terminal cross section 1 Index mark ZD 25 F ZE 100 26 A2 A D E A2 HD HE A A1 bp b1 c c1 c A1 y e *3 bp L L1 Detail F x e x y ZD ZE L L1 Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0 Figure D 100-Pin LQFP (PLQP0100KB-A) Package Dimensions R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 144 of 146 RX62N Group, RX621 Group Appendix 1. Package Dimensions JEITA Package Code P-TFLGA85-7x7-0.65 RENESAS Code PTLG0085JA-A Previous Code TLP-85V MASS[Typ.] 0.1g D wSA wSB x4 v y1 S y S e ZD A K J A S E Reference Symbol Dimension in Millimeters Min Nom 7.0 7.0 Max e H G F E D C B A B D E v w A A1 e b 0.30 x y y1 SD 0.15 0.20 1.20 0.65 0.35 0.40 0.08 0.10 0.2 1 2 3 4 5 6 b 7 8 9 10 ZE xM S A B SE ZD ZE 0.575 0.575 Figure E 85-Pin TFLGA (PTLG0085JA-A) Package Dimensions R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 145 of 146 REVISION HISTORY RX62N Group, RX621 Group REVISION HISTORY REVISION HISTORY Rev. Date RX62N Group, RX621 Group Datasheet Description Summary 1.00 1.10 2011.02.04 2011.02.10 Page -- -- First Edition issued Features reviewed All trademarks and registered trademarks are the property of their respective owners. R01DS0052EJ0110 Rev.1.10 Feb 10, 2011 Page 146 of 146 |
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